Quectel BG96 Manual page 40

Table 12: Pin Definition of UART2 Interface
Pin Name Pin No.
DBG_RXD 22
DBG_TXD 23
Table 13: Pin Definition of UART3 Interface
Pin Name Pin No.
UART3_TXD 27
UART3_RXD 28
The logic levels are described in the following table.
Table 14: Logic Levels of Digital I/O
Parameter
V
IL
V
IH
V
OL
V
OH
The module provides 1.8V UART interface. A voltage-level translator should be used if customers'
application is equipped with a 3.3V UART interface. The voltage-level translator TXS0108EPWR provided
by Texas Instruments is recommended. The following figure shows a reference design.
BG96_Hardware_Design
I/O Description
DI Receive data
DO Transmit data
I/O Description
DO Transmit data
DI Receive data
Min.
-0.3
1.2
0
1.35
LPWA Module Series
BG96 Hardware Design
Comment
1.8V power domain
1.8V power domain
Comment
1.8V power domain
1.8V power domain
Max.
0.6
2.0
0.45
1.8
Unit
V
V
V
V
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