Acer Aspire 7230 Service Manual page 163

POST Code
0x4C Shadow video BIOS ROM if specified by Setup, and
CMOS is valid and the previous boot was OK.
0x59 Register POST Display Services, fonts, and
languages with the POST Dispatch Manager.
0x57 Initialize 1394 Firewire
0xD6 Initialize PC card
0x58 Test for unexpected interrupts. First do an STI for hot
interrupts. Secondly, test the NMI for an unexpected
interrupt. Thirdly, enable the parity checkers and
read from memory, checking for an unexpected
interrupt.
0x3F ROMPolit memory init
0xC4 Install the IRQ vectors (Sever Hotkey)
0x7C Initialize the hardware interrupt vectors from 08 to 0F
and from 70h to 77H. Also set the interrupt vectors
from 60h to 66H to zero.
0x41 ROM Pilot Init
0x4B Initialize QuietBoot if it is installed. Enable both
keyboard and timer interrupts (IRQ0 and IRQ1). If
your POST tasks require interrupts off, preserve
them with a PUSHF and CLI at the beginning and a
POPF at the end.
0xDE Initialize and UNDI ROM (fro remote flash)
0xC6 Initial and install console for UCR
0x4E Display copyright notice.
0xD4 Get CPU branding string
0x50 Display CPU type and speed
0xC9 pretask before EISA init
0x51 EISA Init
0x5A Display prompt "Press F2 to enter SETUP"
0x5B Disable CPU cache.
0x5C Test RAM between 512K and 640K.
0x60 Determine and test the amount of extended memory
available. Determine if memory exists by writing to a
few strategic locations and see if the data can be
read back. If so, perform an address-line test and a
RAM test on the memory.
0x62 The amount of memory available. This test is
dependent on the processor, since the test will vary
depending on the width of memory (16 or 32 bits).
This test will also use A20 as the skew address to
prevent corruption of the system memory.
0x64 Jump to UserPatch1.
0x66 Set cache registers to their CMOS values if CMOS is
valid, unless auto configuration is enabled, in which
case load cache registers from the Setup default
table.
0x68 Enable external cache and CPU cache if present.
Configure non-cacheable regions if necessary.
Chapter 4
Function Phase Component
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
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