Table of Contents
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Oct.2001
CIRCUIT DIAGRAM (MAIN BOARD ASSY/DIGITAL 2)
fig.digital2
D-IN-F2
D-IN-F2
D-IN-F1
D-IN-F1
D-IN-F0
D-IN-F0
D-IN-VF
D-IN-VF
D-IN-DO
D-IN-DO
D-IN-XSTR
D-IN-XSTR
D-IN-ERR
D-IN-DI
D-IN-DI
D-IN-CE
D-IN-CE
D-IN-CL
D-IN-CL
DIN-POW-ON
DIN-POW-ON
GA-DMA-REQ2
GA-DMA-REQ2
GA-DMA-REQ1
GA-DMA-REQ1
GA-DMA-REQ0
GA-DMA-REQ0
GA-DMA-ACK2
GA-DMA-ACK2
GA-DMA-ACK1
GA-DMA-ACK1
GA-DMA-ACK0
GA-DMA-ACK0
CPU-RD
CPU-RD
CPU-UCAS
CPU-UCAS
CPU-LCAS(LWR)
CPU-LCAS(LWR)
CLOCK-OUT
CLOCK-OUT
RESET
RESET
GD-RESET
GD-RESET
LCD_RESET#
LCD_RESET#
CPU-WAIT
CPU-WAIT
CPU-INT
CPU-INT
CS6
CS6
CS5
CS5
CS1
CS1
NF_CS
NF_CS
SM_CS
SM_CS
NF_WP
NF_WP
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
*1 from ZP01300
*2 from ZP34000
38
+
D 3. 3
L29
IC56C
TC7W32F
NF_CS
+
+
D 3. 3
D 3. 3
R61
TR1
10k
1
1
RESET
2
NF_WP
131
130
26
A9
A8
25
A7
24
A6
23
22
A5
A4
21
A3
20
A2
17
A1
16
D15
15
D14
14
D13
13
D12
12
11
D11
D15
D10
10
D14
D9
9
D13
D8
8
7
D12
D7
D11
D6
6
D10
D5
5
D9
D4
4
142
D8
D3
D7
D2
141
D6
D1
140
D5
D0
139
D4
D3
D2
GA-DMA-REQ2
134
D1
GA-DMA-REQ1
133
GA-DMA-REQ0
132
D0
GA-DMA-ACK2
137
GA-DMA-ACK1
136
GA-DMA-ACK0
135
CPU-LCAS(LWR)
27
CPU-RD
28
CS1
29
30
31
CS5
128
129
CPU-WAIT
125
A9
A9
A8
CPU-INT
138
A8
A7
A7
A6
124
A6
A5
A5
A4
A4
CLOCK-OUT
A3
32
A3
A2
A2
A1
A1
A0
GD-RESET
33
A0
110
LCD_RESET#
111
D
123
122
121
120
119
118
117
116
105
115
114
113
112
2
3
+ 5
D
34
35
143
L2
N2012Z601T02
109
144
54
C101
C102
0.1
0.1
C100
C170
C103
100/6.3
0.001
0.1
D
D
+
D 3. 3
IC66
TC74LCX244FT
N2012Z601T02
17
2A4
2Y4
15
2A3
2Y3
13
2A2
2Y2
11
2A1
2Y1
8
1A4
1Y4
C223
6
1A3
1Y3
0.1
4
1A2
1Y2
2
1A1
1Y1
19
2G
1
D
1G
D
IC62
TC7S08F
TR2
CD_CLE
CD_ALE
CD_XRE
4
CD_XWE
C166
CD_XCE
0.1
R73
10k
IC56B
5
TC7W32F
3
6
D
D
IC15
LC24085B-SD1
97
TEST
A19
92
D
A18
XTAL
A9
A8
+
D 3. 3
A7
GA
A6
93
A5
EXTAL
A4
A3
A2
96
CD_SW
A1
SW
76
CD_WP
PROTECT
82
CD_RB
R/B
77
CD_CLE
D15
CLE
78
CD_XCE
D14
CE
79
CD_ALE
D13
ALE
80
CD_XRE
D12
RE
81
CD_XWE
D11
WE
83
CD_XWP
D10
WP
D9
86
CD8
D8
SM-D7
88
CD7
D7
SM-D6
94
CD6
D6
SM-D5
95
CD5
D5
SM-D4
89
CD4
D4
SM-D3
87
CD3
D3
SM-D2
85
CD2
D2
SM-D1
84
CD1
D1
SM-D0
D0
102
MCK
103
BCK
104
DMA-REQ2
LRCK
101
DMA-REQ1
DAOUT1
99
DMA-REQ0
DAOUT0
100
ADIN1
98
ADIN0
DMA-ACK2
DMA-ACK1
DMA-ACK0
75
NC
74
CPU-WR
NC
CPU-RD
CPU-CS
45
XP-CS-IN
SPRX-BCK
44
SM-CS-IN
SPRX-LRCK
46
CD-CS
SPRX-SD
56
XP-CLK
51
XP-SCK
50
D
CD-DETECT
XP-WCK
49
XP-LRCK
WAIT-OUT
52
INT-OUT
XP-SD-AR-TRG
+ 5
D
53
XP-WR-AR-TRG
CPU-WCK
47
WAIT-CA
48
PHAI
WAIT-CB-XP-WAIT
42
RESET
AR-SYNC-WCK
43
WCK-IN
ENC-A
41
ENC-B
PLL-SEND
57
PLL-RTRN
38
PLL-LOCK
40
S2
39
7SEG-D7
S1
D
7SEG-D6
7SEG-D5
60
8
1
EXBV8V101JV
7SEG-D4
LCD-D7
61
7
2
RA1
7SEG-D3
LCD-D6
62
6
3
7SEG-D2
LCD-D5
63
5
4
7SEG-D1
LCD-D4
64
8
1
EXBV8V101JV
7SEG-D0
LCD-D3
65
7
2
RA2
LCD-D2
66
6
3
7SEG-COM4
LCD-D1
67
5
4
7SEG-COM3
LCD-D0
68
R112
7SEG-COM2
LCD-E
69
R104
7SEG-COM1
LCD-RW
70
R84
7SEG-COM0
LCD-RS
58
RESET-CTRL
59
LCD-POWER-UD
106
NC
NC
107
NC
NC
71
NC
NC
NC
NC
18
VDD
37
VDD
73
VDD
90
VDD
VDD
126
VDD
VDD
VDD
C92
C94
0.1
0.1
D
CONTROL[0-50]
D[0-15]
A[0-9]
+
D 3. 3
C304
IC65B
0.1
TC7WH74FU
D
C305
3
SM_XWE
0.1
5
SM_XRE
7
SM_ALE
9
SM_CLE
12
D
14
16
18
64M NAND FLASH
SMART_MEDIA[0-50]
IC29
MBM30LV0064
39
27
NC
I/O7
38
26
NC
I/O6
37
25
+
NC
I/O5
D 3. 3
R182
36
24
NC
I/O4
10k
35
21
NC
I/O3
32
20
NC
I/O2
31
19
NC
I/O1
R186
30
18
NC
I/O0
10k
29
NC
28
NC
17
NC
R187
16
NC
10k
15
13
NC
NC
14
10
NC
NC
9
NC
R188
D 3. 3
8
NC
10k
7
NC
6
NC
D
43
CE
4
44
WE
VCC
42
23
RE
VCCq
5
WP
C121
3
ALE
2
0.1
CLE
40
1
SE
GND
41
22
RY/BY
GND
D
+
D 3. 3
IC60
TC74VHC157F
R175
+
D 3. 3
1k
C231 0.1
R169
C69
10k
0.1
D
12
14
4Y
4A
9
11
D
3Y
3A
7
5
R159
2Y
2A
* 1
4
2
10k
1Y
1A
13
4B
10
3B
1
6
SEL
2B
15
3
ST
1B
R174
10k
D
L51
to ANALOG SIDE
N2012Z601T02
CODEC
R20
L50
100
N2012Z601T02
+
D 3. 3
IC18
R130
TC74VHC164F
L34
100
N2012Z601T02
D
C179
0.1
C158
0.001
D
1
A
5
2
Y
B
C-ADDATA
From ANALOG SID E
3
6
Y
SEL
7
CODEC
ST
INPUT_SEL
IC21
HI: CODEC
TC7WH157FU
LOW:DIGITAL I N
D
LCD+5V
LCD-D7
LCD-D6
L74
RA12
LCD-D5
LCD-D6
9
10
LCD-D4
LCD-D4
8
LCD-D2
7
N2012Z601T02
LCD-D3
LCD-D2
LCD-D0
6
LCD-D1
LCD-RW
5
4
EXBA10E103J
LCD-D0
LCD-RS
100
LCD-E
LCD-E
3
100
LCD-RW
LCD-D1
2
1
100
LCD-RS
10k
LCD-D3
R154
LCD-D5
R155
10k
LCD-D7
R156
10k
D
+
D 3. 3
L1
N2012Z601T02
C98
C169
C99
C104
0.1
0.1
0.1
C95
100/6.3
0.001
D
C217
10/16
R102 100k
CD_XRE
IC65A
R179
TC7WH74FU
10k
2
5
D
Q
+
D 3. 3
1
CK
D
3
Q
R180
10k
CD_XWE
CD_XCE
CD8
CD7
CD_XWP
CD6
CD_WP
CD5
R181
10k
CD4
SM_XRE
R183
10k
CD3
SM_XWE
CD2
R184
10k
CD1
SM_CLE
SM_CLE
R185
10k
SM_ALE
SM_ALE
SM_XRE
SM_XWE
D
1
DIR
19
+
OE
CD1
18
2
B1
A1
CD2
17
3
B2
A2
CD8
16
4
B3
A3
CD3
15
5
B4
A4
CD7
14
6
B5
A5
13
7
CD4
B6
A6
CD6
12
8
B7
A7
CD5
11
9
B8
A8
+
D 3. 3
C122
IC67
10/16
TC74LCX245FT
C306
D
0.1
D
RA30
EXBV8V104JV
C18
* 1
L75
0.1
N2012Z601T02
D
R17
100
+ 5
D
C93
47/6.3(OS)
IC68
TC7SH04
C75
0.001
2
C74
0.1
+ 5
D
13
2
D
QH
B
12
1
QG
A
11
QF
10
5V->
QE
6
QD
5
QC
4
9
QB
CLR
3
8
QA
CK
L22
N2012ZE102T01
* 2
(N2012Z601T02)
+
D 3. 3
IC20A
TC74VHC74F
5
2
Q
D
3
CK
6
Q
From
CPU
0.0
+ 5
D
L38
N2012Z601T
V
G
DIGITAL IN
JK4A
+ 5
D
YKC21-311
C230
+ 5
0.1
IC59
1
D
100
4
R134
2
TC7SET08F
R153
10k
D
D
LCD_D[0-7],LCD_RS,LCD_RW,LCD_E
C207
C208
C209
C4
0.1
0.1
0.1
1/50
C212
C213
C214
C215
0.1
0.1
1/50
1/50
C218
0.1
D
R103
100k
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