General; Timing; Vector Timing; Clock Generation - National Instruments PXIe-6570 Specification

General

Channel count
Multi-site resources per instrument
System channel count
Large Vector Memory (LVM)
History RAM (HRAM)
Maximum allowable offset
(DGS minus GND)
Supported measurement range

Timing

Vector Timing

Maximum vector rate
Vector period range
Vector period resolution
Timing control
Vector period
Edge timing
Drive formats

Clock Generation

Master clock source
Clock domains
1
The system channel count is the maximum number of channels available when using multiple
PXIe-6570 instruments in a single chassis as a digital subsystem. Some functionality described in
this document requires that a PXIe-6674T synchronization module be used in conjunction with
each digital subsystem.
2
If the total voltage sourced or driven on any pin relative to GND exceeds the supported
measurement range, instrument performance may be degraded.
3
Sourced from chassis 100 MHz backplane reference clock, external 10 MHz reference, or
PXIe-6674T.
1
2
32
8
256
128M vectors
1,023 cycles
±300 mV
-2 V to 6 V
100 MHz
10 ns to 40 µs (100 MHz to 25 kHz)
38 fs
Vector-by-vector on the fly
Per channel, vector-by-vector on the fly
Per channel, vector-by-vector on the fly
3
PXIe_CLK100
One (independent clock domains on a single
instrument not supported)
PXIe-6570 Specifications | © National Instruments | 3