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Circuit Description
livery to the modulator on the VCO Unit. If an
external microphone is used, PTT switching is con
trolled by Q2008
(1 MZ1
processor when the impedance at the microphone
If
jack drops.
VOX is enabled, a sample of the
output of the IDC stage is used to activate the
transmitter via Q2010
(DTC124TU).
If
Tone Burst or DTMF is enabled for transmis
sion, the tone is generated by
Q2007 and mixed with transmitter audio at the
IDC stage. Also, the tone is passed via Q2011
to the Motherboard for output to the loud
4215Y)
speaker, as mentioned above. The microprocessor
also disables microphone input to Q2009 via
Q2012 and 02008, and modulator input via Q1003
when transmission is disabled.
(DTC144EU)
The modulating audio is delivered via modula
tion level trimmer VR1001 on the Motherboard to
diode 06005
(188300)
modulating the PLL carrier up to± 5 kHz from the
unmodulated carrier at the transmitting frequency.
Also, if a CTCSS tone is generated by the optional
is
FfS-17 A Unit, it
buffered by Q1001
on the Motherboard, and delivered to the PLL
GR)
Unit with the modulating audio. The modulated
signal from transmitter VCO Q6002
is buffered by Q6005
R22)
delivered to the Motherboard for amplification by
Q1002
(28C3120),
and final amplification by PA
module Q1007
(M67748).
passes through 1/4-wave antenna switch 01011 and
a 3-pole lowpass filter to suppress non-harmonic
radiation before delivery to the antenna.
Automatic Transmit Power Control
RF
power output from the final amplifier is
sampled by C1053 and C1060, and rectified by
01017
). The resulting DC is delivered to
(188321
high/low power controller Q4004
APC Unit, which selects high or two low power
levels via Q4003
(28A 1586Y)
controlled by the microprocessor via
124 TU),
Q2012 on the Control Unit. The output of Q4004 is
inverted by Q4002
(28C4116GR),
Q4001
(288799-ML)
back to the input of final am
plifier Q1007 on the Motherboard, to regulate the
drive level via Q1018
antenna loading conditions and power level selec
If
tion.
the PLL is unlocked, or while receiving, the
INH line causes the ULT5 line to be raised via
Q4008
(DTC144EU),
Q4006
which biases the final amplifier off
(288799-ML),
and disables the front panel keys via Q2014
on the Control Unit.
86)
), which signals the micro
microprocessor
(28C-
on the PLL Unit, frequency
(28C4116-
(28C4226-
and
(28C4226-R22)
The transmit signal then
(FM81)
on the
and Q4005
(DTC-
and passed by
under varying
(8N1 L4M)
(FMW1)
and Q4007
(1 M-
Spurious Suppression
Generation of spurious products by the trans
mitter is minimized by the fundamental carrier
frequency being equal to the final transmitting fre
quency, modulated directly in the transmit VCO.
Additional harmonic suppression is provided by a
lowpass filter consisting of L1006, L1008, L1010
and C1052, C1057, C1059, C1061 and C1066 on the
Motherboard, resulting in more than 60 dB har
monic suppression (for transmitting frequencies in
the amateur band) prior to delivery to the antenna.
PLL Frequency Synthesizer
PLL circuitry on the PLL Unit consists of sepa
rate transmit and receive VCOs (Q6002 and Q6003,
both
and PLL subsystem IC Q6007
28C4226-R22)
(MB1504PF-G-BND),
which contains a swallow
counter, reference oscillator
allel data latch, programmable divider and a phase
comparator. 5-V regulator Q1006
on the Motherboard and filter Q6008
provide the necessary stable supply voltage,
GR)
and temperature compensating capacitors associ
ated with 12.8-MHz frequency reference crystal
X7001 on the Clock Unit provide a stable reference
frequency.
Receiver VCO Q6003 oscillates between 122.3
and 132.3 MHz according to the programmed re
ceiving frequency. The VCO output is buffered by
Q6005
(28C4226-R22),
is buffered by Q6006
(28C4215Y)
I
to the prescaler
swallow counter section of the
PLL chip. There the VCO signal is divided by 64 or
65, according to a control signal from the data latch
section of Q6006, before being applied to the pro
grammable divider section of the chip.
The data latch section of Q6006 also receives
serial dividing data from microprocessor Q2007 on
the Control Unit, which causes the predivided
VCO signal to be further divided by either 19,568
- 21,168 or 24,460- 26,460 in the programmable
divider section, depending upon the desired re
ceive frequency, so as to produce a 5-kHz or 6.25 -
kHz derivative of the current VCO frequency.
Meanwhile, the reference divider section of Q6006
divides the 12.8-MHz crystal reference from the
Clock Unit by 2560 (or 2048) to produce the 5-kHz
(or 6.25-kHz) loop reference (respectively).
The 5-kHz (or 6.25-kHz) signal from the pro
grammable divider (derived from the VCO) and
that derived from the crystal. are applied to the
phase detector section of Q6006, which produces a
dual 5-V pulsed output with pulse duration de
pending on the phase difference between the input
signals. This pulse train is passed to the Clock Unit
FT-26 Technical Supplement
I
divider, serial-to-par
(LM2931AZ-5.0)
(28C4116-
and a sample of the output
for application
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