Sony KDL-32W700B Service Manual page 147

A BOARD SCHEMATIC DIAGRAM (17 OF 24)
1 2 3
A
BROWNIE
R8502 0 1005 CL8505
F4
009:10D TU1_TS_CLK TS_SI_CLK
B CL8506
G3
009:8D TU1_TS_SYNC TS_SI_SYNC
CL8507
CHIP G4
009:8D TU1_TS_VALID TS_SI_VALID
CL8508
F3
009:8D TU1_TS_DATA0 TS_SI_DATA
RB8501
22
D+1.1V
F5
C TSPLLAVD11
C8502 *C8503
XX XX
G5
TSPLLAVS11
GND_D
D
2013/11/29 15:29
[ SEGMENT ]
┌────────┬────────┬────────┐
│ │HE │HM │
├────────┼────────┼────────┤
│C8503 │XX │3300p │
│ │ │50V │
│ │ │X7R │
│ │ │ │
├────────┼────────┼────────┤
│C8505 │XX │7p │
│ │ │50V │
│ │ │CH │
│ │ │ │
└────────┴────────┴────────┘
AYU2-BROWNIE_I/F
E
F
G
H
I
C8500
11p
R8506
2 G 470
V1
XTALO
W1
XTALI
G 1
C8501
J 10p
GND_D
CL8500
F1
OSCEN_X
G2
X_SYSTEM_RST
RST_X
R8501
XX
CL8501
X_BROWNIE_RST V3
CKTESTIN
R8526 CL8502
XX U3
CKTESTOUT
CL8503
T3
TESTEN
CL8504
T4
TESTMODE
K
E12
VDDQ
G1
SLVADR0
GND_D
L
2013/12/05 00:16 5004103813 RB2_BAX_L_PP3_041213.cir/018.sht To PCB System
Chassis RB2G, HE-L
4 5 6 7
Tuner Board I/F connector
TS
CL8512
D1
TS_PI_CLK TS_PI_CLK 009:8D
CL8513
D2 TS_PI_SYNC 009:8D
TS_PI_SYNC
CL8514
D3
TS_PI_VALID TS_PI_VALID 009:8C
CL8515
C1 TS_PI_DAT_0 009:8C
TS_PI_DATA0
C2
TS_PI_DATA1 TS_PI_DAT_1 009:6J
B1 TS_PI_DAT_2 009:6J
TS_PI_DATA2
B2
TS_PI_DATA3 TS_PI_DAT_3 009:6J
A2 TS_PI_DAT_5 009:6J TSIO_DAT_5 =TS_PI_DAT_5
TS_PI_DATA4
=POL_SW
C3
TS_PI_DATA5
TSIO_DAT_4 018:11D
B3
TS_PI_DATA6
TSIO_DAT_6 018:11D
A3
TS_PI_DATA7
TSIO_DAT_7 018:11D
R8530 47
A4
TS_SO1_CLK TSI_CK 018:11D
47
B5 RB8504
TS_SO1_SYNC TSI_STRT 018:11D
C5
TS_SO1_VALID TSI_EN 018:11D
A5
TS_SO1_DATA TSI_DAT 018:11D
R8531 47
C4
TS_SO2_CLK TSIE_CK 018:11E
47
D5 RB8505
TS_SO2_SYNC 1/16W
D4 CHIP
TS_SO2_VALID 5% TSIE_STRT 018:11E
B4
TS_SO2_DATA TSIE_EN 018:11E
TSIE_DAT 018:11E
IC9001
CXD4743GB-T8
R8507 XX
F2
SCL_C I2C_CCP_SCL
R8508 XX
E2
I2C_CCP_SDA
SDA_C
R8509 XX
E1
I2CB_SCL
SCL_D
R8510 XX
E3
SDA_D I2CB_SDA
R8579
C10 XX
AFE_MCLK_A DAUOC_MCLK_CLK
R8580
D10
XX DAUOC_BCK_CLK
AFE_IBCK_A
R8581
D9 XX
AFE_ILRCK_A DAUOC_LRCK_CLK
R8582
D8 XX
DAUOC_DAT_0
AFE_IDATA_A
R8590
D7 XX
DAUOD_MCLK_CLK
AFE_MCLK_B
R8591
C8 XX
AFE_IBCK_B DAUOD_BCK_CLK
R8592
C9 XX
DAUOD_LRCK_CLK
AFE_ILRCK_B
R8593
A7 XX
AFE_IDATA_B DAUOD_DAT_0
R8511 XX
B6
AFE_OBCK DAUIA_BCK_CLK
A6 R8512 XX
DAUIA_LRCK_CLK
AFE_OLRCK
R8513 XX
C6
AFE_OD DAUIA_DAT_0
R8514 0
C7
AFE_IINTR_MUTE_A X_ADAC_MUTE_HPLO
B7 R8515 XX
X_ADAC_MUTE_SCART
AFE_IINTR_MUTE_B
R8516 XX
B16
SPI1_DIN SPIC_DO
A16 R8517 XX
SPIC_DI
SPI1_DOUT
R8518 XX
B15
SPI1_CS SPIC_CS
C15 R8519 XX
SPIC_CK
SPI1_CLK
R8520 XX
A15 SPID_DI
SPI2_DOUT
CL8517
E15 In PWB Design, please put CL8517 at B-side
SPI2_CS
R8522 XX
C14 SPID_CK
SPI2_CLK
B13 VFE_DIO_CLK
CCP_CLK
A13
CCP_DATA_EN VFE_DIO_DEN
D15 VFE_DIO_D9_4
SDVBS_4
D14
SDVBS_3 VFE_DIO_D8_3
E14 VFE_DIO_D7_2 Reserve for interference,
SDVBS_2
the value is TBD.(2012/8/9)
D13
SDVBS_1 VFE_DIO_D6_1
E13 VFE_DIO_D5_0
SDVBS_0 GND_D GND_D
CL8516
D16 In PWB Design, please put CL8516 at B-side
CCP_INTERP1
R8524 XX
B14
CCP_INTERP2 CCP_INT
R8525 XX
A14 PICTURE_MUTE_INT
CCP_INTERP3
IC9001
CXD4743GB-T8
GPIO
CL8509
K1
GPIO0
K2 CL8510
GPIO1
CL8511
H5
GPIO2
H2 R8601 XX
GPIO3 DMD_CLK_ENABLE1
R8602 XX
H3
GPIO4 DMD_CLK_ENABLE2
H4 R8603 XX
GPIO5 DMD_RESET1
R8604 XX
H1
GPIO6 DMD_RESET2
IC9001
CXD4743GB-T8
8 9 10 11 12
To avoid stub connection of W-tuner Serial-TS line and mount variation in this board,
make return path to Tuner Board
To Brownie via TunerBoard
RB8515 0
009:6D TSIO_CK
009:6D TSIO_STRT
009:6C TSIO_EN
009:6C TSIO_DAT_0
To BCAS Connector
009:6J TSIO_DAT_1
X_SCI_DET
009:6J TSIO_DAT_2
SCI_VEN
009:6J TSIO_DAT_3
X_SCI_OCD
009:6J TSIO_DAT_5
TSIO_DAT_5 =TS_PI_DAT_5 =POL_SW
018:7C TSIO_DAT_4
018:7C TSIO_DAT_6
018:7C TSIO_DAT_7
018:6C TSI_CK
TSI_STRT
018:6C
018:6C TSI_EN
TSI_DAT
018:6D
TSIE_CK
018:6D
018:6D TSIE_STRT
TSIE_EN
018:6D
018:6D TSIE_DAT
I2C_CCP_SDA
I2C_CCP_SCL
*** Strap Setting ***
+3.3V_MAIN DAUOA_DAT_0 = STRAP_G[5](InternalPD)
FEIP ES EVA mode (for TSB use)
0:default pin assign
1:FEIP_GPIO pin assign
DAUOC_DAT_0 = STRAP_G[8](InternalPD)
RawNAND PowerSetting
0:VDDO=1.8V
*** Strap Setting *** 1:VDDO=3.3V
□ DAUOD_LRCK = STRAP_G[9](InternalPD)
□ DAUOD_BCK +3.3V_MAIN
= STRAP_G[10](InternalPD)
For Software Use (PCB type ID)
DAUOA_DAT0_HSS
PCBID = b'01
012:7G;012:9G
For board detection of Ryu SW (RB2 Ayu2L)
DAUOC_DAT_0
*** Strap Setting *** 018:6F
DAUOD_DAT_0 = STRAP_G[11](InternalPD)
Ether REFclock setting
0:Ether REFclock output mode
1:Ether REFclock input mode
018:6F DAUOD_BCK_CLK
DAUO_SPDIF_0 = STRAP_G[12](InternalPD) 018:6F DAUOD_LRCK_CLK
JIG mode setting
0:Normal mode
018:6G DAUOD_DAT_0
1:JIG mode
012:7H;009:8J DAUO_SPDIFOP_HSS
+3.3V_MAIN
*** Strap Setting ***
X_ADAC_MUTEC = STRAP_G[0] (InternalPD)
PLL_CPU setting
0:P/M/S=5/0X54/0 806.4MHz
1:P/M/S=5/0X91/1 696.0MHz
+3.3V_MAIN
X_ADAC_MUTED= STRAP_G[1] (InternalPD)
reserved
X_ADAC_MUTE_HPLO
*** Strap Setting *** X_ADAC_MUTE_SCART
SPID_CK = STRAP_G[22](InternalPD)
Debug mode setting
0:debug_mode_off
1:debug_mode_on
SPIC_DO
SPIC_DI
SPIC_CS
SPIC_CK
SPID_DI
SPID_CK
004:15G MS_SCK
R8538 0 VFE_DIO_CLK
004:15G MS_DATA
R8539 0 VFE_DIO_DEN
004:15G MS_BS
R8540 0 VFE_DIO_D9_4
VFE_DIO_D8_3
VFE_DIO_D7_2
VFE_DIO_D6_1
VFE_DIO_D5_0
X_AUDIO_MUTE_SPHPLO
X_AUDIO_MUTE_SCART
VFE digital :
Please put VFE bus on Layer-3 for EMI/interfarence C/M.
R8570-R8576:
if possible on PWB design, please put close to Brownie(IC9001).
13 14 15 16
AYU2
XX
R8545
XX TSIO
RB8514
AF1
TSIO_CK/GPIO_52/SCI_CK/SCI_TDA_CLK
AF2
TSIO_STRT/GPIO_54/SCI_DI/SCI_DIO
AF3
TSIO_EN/GPIO_53/SCI_RST/SCI_RST
XX
RB8510 AG1
TSIO_DAT_0/GPIO_55/SCI_DOEN
AG2
TSIO_DAT_1/GPIO_56/SCI_DET/SCI_DET
AG3
TSIO_DAT_2/GPIO_57/SCI_VEN/SCI_CMDVCC
AH1
TSIO_DAT_3/GPIO_58/SCI_OCD/SCI_CLKDIV
XX
RB8511 AJ1
TSIO_DAT_4/GPIO_59
AH2
TSIO_DAT_5/GPIO_60
AJ2
TSIO_DAT_6/GPIO_61
AK2
TSIO_DAT_7/GPIO_62
R8548 XX
AJ13
TSI_CK
AH14
TSI_STRT
AG14
TSI_EN
AJ14
TSI_DAT
R8549 XX
AJ12
TSIE_CK
AG13
TSIE_STRT
AH13
TSIE_EN
AK12
TSIE_DAT
*IC9000
CXD4748GB
2013/11/29 15:29
[ SOC ]
+3.3V_MAIN ┌────────┬────────┬────────┐
│ │60 │60AVS │
├────────┼────────┼────────┤
│IC9000 │CXD4748GB │CXD4748GB-1 │
└────────┴────────┴────────┘
AYU2L-BROWNIE_I/F
R8554 XX
AD3
I2C_CCP_SDA
R8555 0
AE3
I2C_CCP_SCL
*** Strap Setting ***
DAUOC_LRCK = STRAP_G[6](InternalPD)
DAUOC_BCK = STRAP_G[7](InternalPD)
->Strap setting at PERI(STBY)
R8556 XX
AJ18
DAUOC_MCLK_CLK DAUOC_MCK
R8557 XX AH18
DAUOC_BCK_CLK
DAUOC_BCK
R8558 XX For HP/Line Out
AK17
DAUOC_LRCK_CLK DAUOC_LRCK
R8559 XX AJ17
DAUOC_DAT_0
R8560 XX AH17
DAUOD_MCLK_CLK
DAUOD_MCK
R8561 XX
AJ16
DAUOD_BCK
R8562 XX AG17 For SCART Out
DAUOD_LRCK
R8563 XX
AH16
DAUOD_DAT_0
AH15
DAUIA_BCK_CLK DAUIA_BCK
AJ15
DAUIA_LRCK_CLK For Analog Input
DAUIA_LRCK
AK14
DAUIA_DAT_0 DAUIA_DAT_0
R8552 0 Brownie Audio DAC Mute
AK15
X_ADAC_MUTEC
R8553 XX
AG16
X_ADAC_MUTED
R8565
XX
47 AJ22
MS_BS/SPIC_DO
RB8517
AK21
SPIC_DI
For CI Transfer
AK22
MS_DATA/SPIC_CS
AH22
MS_SCK/SPIC_CK
R8568 XX
AJ21
SPID_DI VFE digital :
The reserve C-lands for EMI.
Slice Data from Brownie
R8569 XX
AH21
SPID_CK D+1.1V
R8570 47
AK20
VFE_DIO_CLK
R8571 47
AJ20
VFE_DIO_DEN
R8572 47 C8506 C8507 C8508
AH20 XX XX XX
VFE_DIO_D9_4
AK19 SD Video
VFE_DIO_D8_3
AYU2 -> Brownie :
AJ19
VFE_DIO_D7_2
Brownie -> AYU2 :
AH19
VFE_DIO_D6_1
GND_D
AK18
VFE_DIO_D5_0
RB8518
47
R8577 XX
AG5
X_AUDIO_MUTEC C : SP/HP Out Mute
R8578 XX
AF4 D : SCART Out Mute
X_AUDIO_MUTED
R8550 XX
A4
MS_INS_X MS_INS_X/GPIO_37
Memory Stick
004:15H C5
MS_PON MS_PON/GPIO_36
R8551 XX
004:15H
*IC9000
CXD4748GB
ORIGINAL
MODEL BAX_L BOARD
DESCRIPTION
AYU2-BROWNIE I/F
PART NO.
RB2
ALL resistors are in ohms,W unless otherwise noted.
ALL capacitors are in uF(p:pF)unless otherwise noted.
Chassis RB2G, HE-L
SHEET
18/18
147