Sony KDL-32W700B Service Manual page 136

A BOARD SCHEMATIC DIAGRAM (6 OF 24)
1 2 3
I = 1A
40m ohm_@Vgs=-2.5V
A
STBY_+3.3V +3.3V_NAND
Q1001
PMV32UP
R1010
XX
R1003
100k
R1012
XX
C1000 R1008
0.1 10k GND_D
1005
005:9B
NAND1_PWR Q1000
B PDTC144EU
GND_D
FET SW for RawNAND
C
+3.3V_MAIN [Strap][Flash Construction Settings]
SPID_DI:SPIC_DI
=STRAP_G[14:13]
"Boot" "Bit Width"
=11: RawNAND 8x2
=10: RawNAND 16x1
=01: RawNAND 8x2
=00: RawNAND 8x1
Current Setting: [ALL] 00
018:6H;018:11I
SPID_DI
018:6G;018:11H
SPIC_DI
D
E
F
G
H
I
J
K
L
2013/12/05 00:16 5004103813 RB2_BAX_L_PP3_041213.cir/006.sht To PCB System
Chassis RB2G, HE-L
4 5 6 7 8
+3.3V_MAIN
FIF
PLEASE PUT B-side
CL1008 RB1000 FIF_RND_DAT[0]
AB18 AG30 68
VDD_NAND RND_IO_0/RND_IO_0
AB19 AG29 CL1009 FIF_RND_DAT[1]
VDD_NAND RND_IO_1/RND_IO_1
CL1010 FIF_RND_DAT[2]
AC18 AF28
VDD_NAND RND_IO_2/RND_IO_2
AC19 AH30 CL1011 FIF_RND_DAT[3]
VDD_NAND RND_IO_3/RND_IO_3
CL1012 RB1001 FIF_RND_DAT[4]
AG28 68
RND_IO_4/RND_IO_4
AH29 CL1013 FIF_RND_DAT[5]
RND_IO_5/RND_IO_5
STBY_+3.3V
GND_D CL1014 FIF_RND_DAT[6]
AJ30
RND_IO_6/RND_IO_6
C1007
XX H18 AH28 CL1015 FIF_RND_DAT[7]
VDD_NAND_STBY RND_IO_7/RND_IO_7
AF27
GND_D GPIO_3/RND_IO_8 GPIO_3 004:7E
AJ27
GPIO_4/RND_IO_9 GPIO_4 004:7E
AK27
GPIO_9/RND_IO_10 GPIO_9 004:7E
AH26
GPIO_10/RND_IO_11 GPIO_10 004:7E
AJ26
GPIO_11/RND_IO_12 GPIO_11 004:7F
AK26
GPIO_14/RND_IO_13 GPIO_14 004:7F
AG26 GPIO_15 004:7F
GPIO_15/RND_IO_14
AF26
GPIO_16/RND_IO_15 GPIO_16 004:7F
For upper NAND data line
CL1016
AH27 FIF_RND_RE_X
RND_RE_X/RND_RE_X
CL1017 R1022 FIF_RND_WE_X
AJ29 47
RND_WE_X/RND_WE_X
CL1018
AK28
RND_RB/RND_RB
AJ28 CL1019
RND_ALE/RND_ALE
CL1020
AK29
RND_CLE/RND_CLE
AE26 RB1009 47 FIF_RND_CLE
GPIO_35/RND_TEST_0 GPIO_35 004:7G
AE27
GPIO_44 004:7G Integrate Dumping R to RB
SYNC_4K2K/RND_TEST_1/GPIO_44
for cost down
A24
STBY_RND_CE0_X/STBY_RND_CE0_X
B17 STBY_GPIO_19 005:12C
STBY_SPIA_DO/STBY_GPIO_19/STBY_RND_CE1_X
R1019
CL1021 FIF_RND_WP_X
For cascade toporogy 47
CL1022 R1020 FIF_RND_CE_X
47
WP and CE are STBY domain line.
B24
Each R is put near STBY domain.
STBY_RND_WP_X/STBY_RND_WP_X
*IC9000
CXD4748GB
2013/07/05 18:18
┌────────┬────────┬────────┐ [ SOC ]
│ │60 │60AVS │
├────────┼────────┼────────┤
│IC9000 │CXD4748GB │CXD4748GB-1 │
└────────┴────────┴────────┘
9 10 11 12
+3.3V_NAND +3.3V_NAND
FIF_RND_RB FIF_RND_RB
FIF_RND_ALE
RB1002
47K
GND_D
+3.3V_NAND
Integrate PullUp/Down R to RB
for cost down
GND_D
13 14 15 16
RawNAND_0_lower
+3.3V_NAND +3.3V_NAND
TC58NVG3S0FTAI0B4Q
IC1000
NC NC
NC NC
NC NC
RB1007
68
NC NC
CL1045
FIF_RND_DAT[7]
NC IO7
CL1046 FIF_RND_DAT[6]
NC IO6
R1037 CL1038 CL1047
FIF_RND_RB 0 FIF_RND_DAT[5]
R/B# IO5
FIF_RND_RE_X R1038 CL1039 CL1048 FIF_RND_DAT[4]
0
RE# IO4
CL1040
FIF_RND_CE_X
CE# NC C1013
R1039 0.1
XX NC NC
C1012 NC NC C1014
0.1 XX
VCC VCC
VSS VSS
NC NC C1015
GND_D XX
NC NC
FIF_RND_CLE R1040 CL1041
0
CLE NC
FIF_RND_ALE R1041 CL1042 CL1049 FIF_RND_DAT[3]
0
ALE IO3
R1042
FIF_RND_WE_X CL1043 CL1050 FIF_RND_DAT[2]
0
WE# IO2
FIF_RND_WP_X R1043 CL1044 CL1051 FIF_RND_DAT[1]
0
WP# IO1
CL1052 FIF_RND_DAT[0]
NC IO0
NC NC 68
NC NC RB1008
NC NC
NC NC
For Micron
25:NC -> GND GND_D
48:NC -> GND
34:NC -> VCC
39:NC -> VCC
ORIGINAL
MODEL BAX_L BOARD
DESCRIPTION
FLASH MEMORY INTERFACE
SHEET
PART NO.
RB2
ALL resistors are in ohms,W unless otherwise noted.
6/18
ALL capacitors are in uF(p:pF)unless otherwise noted.
Chassis RB2G, HE-L
136