Yaesu FT-2400H Technical Supplement page 8

Transmit Signal Path
Speech input from the microphone is delivered
via the Mic (Jack) Unit and the Control Unit to the
Interface Unit, where it passed through Mic Mute
analog switch Q3009
and pre-emphasis by Q3007
vent over-deviation, the audio is processed by IDC
(instantaneous deviation control) stage Q3007- % ,
and then lowpass filtered by Q3008
&
-1/4) before delivery to the modulator on the VCO
Unit. Q3007- % provides a low impedance refer­
ence for the lowpass filter input and some of the
other opamps.
If
a CTCSS tone is enabled for transmission, the
subaudible tone from microprocessor Q2001 on the
Control Unit is lowpass filtered by Q3007- % and
mixed with the !DC-processed speech audio. Also,
DTMF tones generated by the FRC-6 option (con­
nected to the P RC Unit jack), or directly from the
microprocessor, are applied to the transmit audio
c h ain at the input of the IDC stage. The microproc­
essor also disables microphone at Mic Mute switch
Q3009 via Q3010
The modulating audio is delivered to diode
D305 (HVU202)
ulating the PLL carrier up to ± 5 kHz from the
unmodulated carri e r at the transmitting frequency.
The modulated signal from transmitter VCO Q303
is buffered by Q305
(MMBR951 L)
delivered to the Main Unit for amplification by
Q1012
(2SC2759),
(2SC2538). The low level transmit signal. is then
finally amplified by PA module Q1009
to 50 watts. Harmonic spurious radiation in the
final output is suppressed by a 3-pole lowpass fil­
ter on the Main Unit, and the transmit signal then
passes through % -wave antenna switch D1016 be­
fore delivery to the antenna.
Automatic Transmit Power Control
RF
power output from the final amplifier is sam­
pled by C1064 and rectified by D1017
The resulting DC
power controller Q1017
hibit gate Q1018
troller Q1019 (2SB986S)
voltage to transmitter RF amplifiers Q1010 and
QlOl 1, so as to maintain stable high, medium or
low output power under varying antenna loading
2-2 conditions.
CIRCUIT DESCRIPTION
(TC4S66F) for amplification
(LA6324M-%).
(LA6324M-%
when necessary.
(DTC114EK)
on the VCO Unit, frequency mod­
(2SC2759)
Q1011
(MMBR951L)
(S-AV24)
is
passed by high/medium/low
(FMS1) and transmit in­
(IMX1) to Automatic Power Con­
which regulates supply
Spurious Suppression
Generation of spurious products by the trans­
mitter is minimized by t he fondamental carrier
·
frequency being equal to the final transmitting fre­
quency, modulated directly in the transmit VCO.
Additional harmonic suppression is provided by a
To pre­
3-pole lowpass filter consisting of Ll002, L1013,
L1014 and C1002, C1062f C1063, C1065-C1067,
C1152 and C1153, resulting in more than 60 dB
harmonic suppression (for transmitting frequen­
cies in the amateur band) prior t o delivery to the
antenna.
PLL Frequency Synthesizer
PLL circuitry on the Main Unit consists of swal­
low counter Q1025
system IC Q1024
reference oscillator I divider, serial-to-parallel data
latch, programmable divider and a phase com­
parator. Stability is obtained by a regulated 5-V
supply via Q1014
perature compensating capacitors associated with
12.8-MHz frequency reference crystal X1002.
Receiver VCO Q301
Unit os�illates between 118.6 and 152.6 according
to the programmed receiving frequency. The VCO
output is buffered by Q305
Unit, and then returned to the Main Unit where a
sample of the output is buffered by Q1028
for application to prescaler I s wallow
2714)
and
counter Q1025. There the VCO signal is divided by
64 or 65, according to a control signal from the data
and Q1010
latch section of Q1024, before being applied to the
programmable divider section of the PLL chip.
up
The data latch section of Q1024 also receives
serial dividing data from microprocessor Q2001 on
the Control Unit, which cau s es the predivided
VCO sig n al to be further divided by 23,720 -
30,520 ill the programmable divider section, de­
pending upon the desired rec e! ve frequency, so as
to
produce a 5-kHz or 6.25-kHz derivative of the
current VCO frequency. Meanwhile, the reference
divider sec�ion of Q1024 divides the 12.8-MHz
(1SS108).
crystal reference by 2560 (or 2048) to produce the
5-kHz (or 6.25-kHz) loop reference (respectively).
The 5-kHz (or 6.25-kHz) signal from the pro­
grammable divider (derived from the VCO) and
that derived from the crystal are applied to the
phase detector section of Q1024, which produces a
dual 5-V pulsed output with pulse duration de­
pending on the phase difference between the input
(MC12022SLAD) and PLL sub­
(MC145158F2), which contains a
(2SC2712GR) to Q1024 and tem­
(MMBR951 L) on the VCO
(2SC2759) on the VCO
(2SC-