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I/O CHART OF IC3201
Pin No.
I/O
Signal Name
Description
A1
-
DVSS
Ground
A2
-
GESW
(Not used)
A3
I
XRST
Reset : low
A4
-
TSTDT[9]
(Not used)
A5
-
TSTDT[6]
(Not used)
A6
-
TSTDT[3]
(Not used)
A7
-
TSTDT[0]
(Not used)
A8
O
REQR
Request of R10
A9
I/O DVR[2]
Digital Rec/PB data (2)
A10
I/O
DVR[0]
Digital Rec/PB data (0)
A11
-
DVSS
Ground
B1
-
VRH
V-ref : high
B2
-
VRL
V-ref : low
B3
-
TSTMD
(Not used)
B4
I
VPD
+1.8V
B5
-
DVSS
Ground
B6
-
TSTDT[4]
(Not used)
B7
-
TSTDT[1]
(Not used)
B8
I
ACKR
Acknowledge for R10
B9
I/O DVR[3]
Digital Rec/PB data (3)
B10
I/O DVR[1]
Digital Rec/PB data (1)
B11
I
CLK27A
27MHz clock
C1
I
AVD12 (ADC1)
+1.8V
C2
-
ADTEST
Test pin
C3
-
AVS12 (ADC1)
Ground
C4
-
CS
(Not used)
C5
-
TSTDT[8]
(Not used)
C6
-
TSTDT[5]
(Not used)
C7
-
TSTDT[2]
(Not used)
C8
-
TSTCKI
(Not used)
C9
I
DVDD18
+1.8V
C10
I
XWEL
Write enable
C11
I
XRE
Read enable
D1
I
AVD14 (AMP1)
+1.8V
D2
-
AVS14 (AMP1)
Ground
D3
I
PBIN
PB data input (+)
D4
I
AVD15 (ADC2)
+1.8V
D5
I
DVDD18
+1.8V
D6
-
TSTDT[7]
(Not used)
D7
I
DVDD18
+1.8V
D8
-
DVSS
Ground
D9
I
XWEH
Write enable
D10
I
AS
Address strobe
D11
I/O ADM[15]
Address/data 15
E1
I
ATFIN
ATF input
E2
-
AVS15 (ADC2)
Ground
E3
I
AVD13 (ADC1/2)
+1.8V
E4
-
AVS13 (ADC1/2)
Ground
E8
I
DVDD18
+1.8V
E9
I/O ADM[14]
Address/data 14
E10
-
DVSS
Ground
E11
I/O ADM[12]
Address/data 12
F1
I
AVD16 (VREF)
+1.8V
F2
-
VCORP
VCO reference resister
F3
-
AVS16 (VREF)
Ground
F4
-
VREF3
V-ref3
Pin No.
I/O
Signal Name
Description
F8
I/O ADM[13]
Address/data 13
F9
I/O ADM[11]
Address/data 11
F10
I/O ADM[10]
Address/data 10
F11
I/O ADM[9]
Address/data 9
G1
-
AVS22 (DAC2/3)
Ground
G2
O
OSO
Offset output
G3
-
VREF2
V-ref2
G4
-
VREF1
V-ref1
G8
I
DVDD18
+1.8V
G9
I/O ADM[8]
Address/data 8
G10
I/O ADM[7]
Address/data 7
G11
I/O ADM[6]
Address/data 6
H1
I
AVD22 (DAC2/3)
+1.8V
H2
O
ATF0
ATF output
H3
I
AVD21 (DAC1)
+1.8V
H4
-
DVSS
Ground
H5
O
TDO
Test data In of JTAG
H6
O
RECI
Rec on/off control
H7
I
DVDD18
+1.8V
H8
-
DVSS
Ground
H9
I/O ADM[5]
Address/data 5
H10
I/O ADM[4]
Address/data 4
H11
I/O ADM[3]
Address/data 3
J1
O
FPORP
Frequency Phase out (+)
J2
-
AVS21 (DAC1)
Ground
J3
O
RECCUR
Rec current control
J4
O
CAPRSF
Capstan motor Reverse(H)/Stop(M)/Forward(L)
J5
I
TDI
Test data out of JTAG
J6
O
HID2
Head switch pulse 2
J7
I
EQHLD
Equalizer hold
J8
I
CYLFG
Cylinder FG head
J9
I
ADD18
+1.8V
J10
I/O ADM[2]
Address/data 2
J11
-
ADM[1]
(Not used)
K1
-
FRP
(Not used)
K2
I
AVD11 (VCO)
+1.8V
K3
O
AGCCTL
AGC control
K4
O
CYLERR
Cylinder error
K5
I
TMS
Test mode of JTAG
K6
O
HID1
Head switch pulse 1
K7
-
DVSS
Ground
K8
O
RECCLK
Rec clock
K9
O
PBH
PB mode : high
K10
-
ADM[0]
(Not used)
K11
I
CYLPG
Cylinder PG head
L1
I
VCOIN
VCO input
L2
-
AVS11 (VCO)
Ground
L3
I
DVDD25
+2.5V
L4
O
CAPERR
Capstan error
L5
I
TRST
Reset : low
L6
I
TCK
Test clock of JTAG
L7
O
SPA
Sample pulse for ATF
L8
O
HSE
Rec data
L9
O
RECCTL
Rec control
L10
O
DriveCLK
Drive clock
-
DVSS
Ground
L11
33
IC5001 IC- DETAIL BLOCK DIAGRAM
44
43
42
41
40
39
38
GND
GND
ENVE
DET
1
LPF
2
GND
AMP
3
4
AGC
AGC
DET
5
VCC
(+3V)
6
7
8
LOGIC
DRIVE
GCA
9
10
11
LOGIC
GND
12
13
14
15
16
17
18
PV-GS80P/PV-GS80PC/PV-GS83P/PV-GS85P/PV-GS85PC
37
36
35
34
VCC
(+5V)
33
CH2
32
CH1
31
30
29
28
CH2
27
CH1
26
25
24
23
VCC
(+1.8V)
19
20
21
22
I/O CHART OF IC3201
IC5001 IC-DETAIL BLOCK DIAGRAM
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