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7. CIRCUIT DIAGRAM
1
1
2
2
3
3
A
A
TCC_2.6V_MISC
B
B
TCC_RESET_N
EBI2_DATA[0:15]
EBI2_DATA[15]
EBI2_DATA[14]
C
C
EBI2_DATA[13]
EBI2_DATA[12]
EBI2_DATA[11]
EBI2_DATA[10]
EBI2_DATA[9]
EBI2_DATA[8]
EBI2_DATA[7]
EBI2_DATA[6]
EBI2_DATA[5]
EBI2_DATA[4]
EBI2_DATA[3]
EBI2_DATA[2]
EBI2_DATA[1]
EBI2_DATA[0]
LCD_BYPASS_ENABLE
TCC_CS_N
TCC_SUB_CS_N
EBI2_WE_N
D
D
EBI2_OE_N
active HIGH
TCC_INT
EBI2_ADDR[1]
R816
DIB_RESET_N
100K
DIB_RDY
DIB_ADDR[2]
DIB_ADDR[1]
DIB_PWR_EN
DIB_CS_N
DIB_WE_N
SRAM like I/F
DIB_OE_N
DIB_DATA[7]
DIB_DATA[6]
DIB_DATA[5]
DIB_DATA[4]
DIB_DATA[3]
DIB_DATA[2]
DIB_DATA[1]
DIB_DATA[0]
E
E
UART
TCC_UART_TXD
TCC_UART_RXD
F
F
DIB_IRQ
TCC_TDO
TCC_TMS
JTAG I/F
TCC_RTCK
G
G
TCC_TDI
TCC_TCK
TCC_NTRST
H
H
1
1
2
2
3
3
Copyright © 2008 LG Electronics. Inc. All right reserved.
Only for training and service purposes
4
4
5
5
6
6
TCC_1.2V_CORE
TCC_2.7V_EHI_LCD
TCC_2.6V_SDR
TCC_2.6V_MISC
C819
C820
12p
12p
X801
DSX321G(12MHz,8PF)
3
4
2
1
12MHz
TCC_2.6V_MISC
R800
TCC_2.7V_EHI_LCD
1M
TCC_1.2V_CORE
TCC_2.6V_SDR
R803
TV_OUT_3.0V
100K
J3
F4
HPXD17
LPD_23
K1
F3
HPXD16
LPD_22
K3
F2
HPXD15
LPD_21
L2
G7
HPXD14
LPD_20
H6
G6
HPXD13
LPD_19
L1
G1
HPXD12
LPD_18
K4
A2
HPXD11
LPD_17
L3
A1
HPXD10
LPD_16
J5
A3
HPXD9
LPD_15
L4
D6
HPXD8
LPD_14
M1
E6
HPXD7
LPD_13
M2
C4
HPXD6
LPD_12
M3
D5
HPXD5
LPD_11
J6
B3
HPXD4
LPD_10
N1
B1
HPXD3
LPD_9
K5
B2
HPXD2
LPD_8
K6
C3
HPXD1
LPD_7
N2
C2
HPXD0
LPD_6
D4
LPD_5
G3
D3
BPEN
LPD_4
J2
D2
HPCSN
LPD_3
H2
E5
HPCSN_L
LPD_2
J1
D1
HPWRN
LPD_1
K2
E4
HPRDN
LPD_0
H3
HPINTO
H5
HPXA1
H4
HPXA0
N3
R814
SDCKE
N11
10K
GPIO_B15
J10
U807
GPIO_B14
J9
E1
GPIO_B13
LCSN0
K10
F6
GPIO_B12
LCSN1
TCC7920S
L10
E2
GPIO_B11
LOEN
L9
E3
GPIO_B10
LWEN
K9
F7
GPIO_B9
LXA0
N8
GPIO_B8
L8
GPIO_B7
M8
M4
GPIO_B6
SCMD0
K7
N5
GPIO_B5
SCLK0
L7
M5
GPIO_B4
SDI0
4.7K
N7
N4
GPIO_B3
SDO0
M7
GPIO_B2
R818
N6
GPIO_B1
M6
GPIO_B0
B9
M9
UTXD0
SCMD1
A9
N9
URXD0
SCLK1
F8
M10
UCTS0
SDI1
R819
C9
N10
URTS0
SDO1
4.7K
A8
UTXD1
E8
URXD1
B8
UCTS1
C8
B6
URTS1
BCLK
E7
LRCK
C7
A6
UTXD2
MCLK
B7
C6
URXD2
DAO
A7
C5
UTXD3
DAI
D8
URXD3
B5
GPIO_A0
A5
GPIO_A1
L6
G4
GPIO_A4
GPIO_F27
L5
G5
GPIO_A5
GPIO_F26
N12
H1
GPIO_A6
GPIO_F25
M13
GPIO_A7
N13
GPIO_A8
M11
BM[2:0]
GPIO_A9
000b
M12
GPIO_A10
EHI boot mode
L13
F5
GPIO_A11
GPIO_C30
L12
G2
GPIO_A12_CDATA
GPIO_C31
TV_OUT_3.0V
TV OUT
L801
TV_OUT
R832
3.3uH
12K
R897
C827
C828
270p
270p
39
R835
10K
4
4
5
5
6
6
7 7
8
8
9
9
U?
FSA4157L6X
6
1
B1
S
LCD_BYPASS_ENABLE
5
2
GND
VCC
4
3
B0
A
+3.0V_AUDIO
TCC_PWR_EN
MM_LCD_DATA[15]
MM_LCD_DATA[14]
MM_LCD_DATA[13]
MM_LCD_DATA[12]
MM_LCD_DATA[11]
MM_LCD_DATA[10]
MM_LCD_DATA[9]
MM_LCD_DATA[8]
LCD I/F
MM_LCD_DATA[7]
MM_LCD_DATA[6]
MM_LCD_DATA[5]
MM_LCD_DATA[4]
MM_LCD_DATA[3]
MM_LCD_DATA[2]
MM_LCD_DATA[1]
MM_LCD_DATA[0]
MM_MAIN_LCD_CS_N
MM_SUB_LCD_CS_N
MM_LCD_RD_N
MM_LCD_WE_N
MM_LCD_ADS_N
SDO1
SDO0
JTAG selection
0
0
ARM926 Main
0
1
Test mode (Not used)
1
0
ARM926 Sub
1
1
Both core
Always on state
BCLK
CODEC I/F
LRCK
MCLK
DA_OUT
EHI_LCD LDO & CAPS Removed
MM_LCD_VSYNC
7
7
8
8
9
9
- 159 -
10
10
11
11
12
12
LGE Internal use only
A
A
B
B
TCC7920S Power
TCC_1.2V_CORE
+VPWR
U802
AAT1143IJS-0.6-T1
C
C
1
8
EN
PGND3
R815
2
7
OUT
PGND2
56K
( 1% )
3
6
VIN
PGND1
L900
4.7uH
4
5
LX
AGND
100p
C821
( 400mA )
C823
C822
2.2u
4.7u
( 1% )
TCC_2.6V_SDR
D
D
TCC_2.6V_MISC
+VPWR
U803
R1131D261D
6
1
CE
VDD
5
2
GND
NC1
4
3
NC2
VOUT
C824
C825
C826
( 300mA )
1u
1u
2.2u
E
E
TCC_2.7V_EHI_LCD
VREG_MSMP_2.7V
R830
F
F
0
G G
H
H
10
10
11
11
12
12
LGE Internal Use Only
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