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4-2.
OSCILLATOR CIRCUIT
The clock (IC604-1) is generated by attaching crystal oscillator (23 MHz) to IC604 outside. This clock is matched the
phase at rising down of H-SYNC when fetching the video signal. At that time, the clock signal is disordered. It is corrected
at the circuit (IC601, IC605) to reduce the noise. Memory control and etc. are performed by this clock (IC601 pin 25) as
master clock.
Oscillator Circuit
1
H-SYNC
(IC601-4)
X601
(23 MHz)
H-SYNC
SCLK
(usual)
SCLK
(when fetching)
4-3. IC601 PERIPHERAL CIRCUIT
IC601 consists of following blocks.
(1) Register for serial data storing from system control (IC505)
1 Various mode setting
2 SYNC signal processing parameter
3 Coefficient for scaling calculation
4 Gamma data
(2) Frame memory write and read control
(3) Thermal head control
(4) SYNC signal processing circuit
(5) 1 line memory (for print)
(6) Image scaling calculation circuit
Each block operation is decided by serial data from system control (IC505) and mode switching terminal.
UP-960(UC)
UP-960CE(CE)
32
3
DELAY
35
6
IC
IC606
10
CXD
8932Q
13
12
Phase matching
——— 22 byte
——— 4 byte
——— 128 byte
——— 34 byte
21
22
25
23
CXD 8726R
23
1
Phase matching
SCLK
(SAMPLING CLOCK)
4-5
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