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3-4. BLOCK DIAGRAM — MPEG SECTION —
CD-DATA
CD PCMD
180
CD
CD-BCK
A
CD BCK
184
SECTION
CD-LRCK
CD LRCK
182
(Page 20)
CD-C2PO
185
PROGRAM
13
RESET
ROM-CS
128
MEMORY
CONTROL
LDQM
79
MWE
82
SD-CAS
85
SD-RAS
86
SD-CS0
90
SD-CLK
84
UDQM
80
53,54,56,58-60
62,64,66,68,70
72-74,76,78
2,3,5,6,8,9
19-24
11,12,39,40,42
27-32
43,45,46,48,49
A0-10,BA
DQ0-15
14 15 16 17 18
35
36
MPEG DECODER
IC514
CD-DA
DA-DATA1
DEC
DA-BCK
DA-LRCK
AUDIO
MPEG
DA-XCK
DIGITAL
DSP
AUDIO
AUDIO
DEC
I/F
HSYNC
VSYNC
LYLICS
STREAM
DEC
DEC
VDATA0-7
MPEG
VIDEO
AUDIO
MIX
DEC
OSD
DEC
VCLK
HOST
SYSCLK
I/F
HADDR0-2
HDATA0-7
MADDR0-18
WAIT
96,98-100,102,104-106
2-4,6
108,110-112,114,116
202 - 204
8-11
118,120-122,124
1-6
21-23
9-20,31
25-29
Q0-7
A0-18
30
ROM
SDRAM
IC521
IC520
(Page 20)
163
DA DATA
CD
167
DA BCK
B
166
DA LRCK
SECTION
VIDEO ENCODER
169
DA XCK
HSYNC
HS
157
1
VS
VSYNC
158
28
YCRCB
DATA
0-7
VD0-7
MANAGER
UNIT
CKREF
24
RESET
IC519
25
,
X
tal OSC
177
4
2
178
X514
27MHz
CD SYSTEM CONTROL
IC513 (2/2)
CS
206
94
71
H_CS
TV_RST
R/W
207
89
H_R/W
RD
90
208
H_RD
SDA
9
15
11
H_WAIT
SCL
10
INT
16
12
H_INT
CD_ON
3
CDM_ON
100
HADDR
HA0-2
0-2
XTAL
40
X511
12MHz
EXTAL
41
HDATA
HD0-7
MSC
79
0-7
MSI
78
1
BUFFER
IC523
MSO
77
32
MSRQ
MCS
80
RESET
38
D515
A_MUTE
1
75
BU_IN
D516
96
H_RST
21
21
Signal path
: CD AUDIO
: VIDEO
IC518
VIDEO
AMP
IC551
75Ω
PJ101 (1/2)
DRIVER
CVBS
VIN1
VOUT1
-3
DAC
11
1
4
2
I
C CONTROL
+6dB
3
LOGIC
VCC
7
27
26
POWER
SWITCH
Q513,514
VIDEO +5V
CD ON
MAIN
E
SECTION
(Page 22)
MECHA ON
MSC
7
MSI
MAIN
F
SECTION
(Page 22)
MSO
MSRQ
MCS
SYS RESET
A MUTE
MAIN
G
SECTION
(Page 22)
BU CHECK
CSX-V58MP
VIDEO OUT
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