Multiplexor Storage Bus Or'ing; Multiplexor Address Switches; Data Flow And Control; Cpu To Core Storage - IBM 7090 Instruction-Reference

4.1.03 Multiplexor Storage Bus OR ling
All data going to core storage are routed through the multiplexor storage bus OR ling
circuits. See Figure 4.1-3. These circuits consist of OR circuits that multiplex data
coming from either bank of the data channels or the CPU. Positions S, 1-35 of the CPU
storage register are logically OR led with positions S, 1-35 of both banks of channel
storage bus switches. This provides the proper isolation between the three sets of in-
puts to the bus, and allows for the proper matching of the output.
It
is important to notice that data being routed through these circuits are gated at the
CPU storage register or the channel storage bus switches.
The output of the OR circuits consists of 36 (S, 1-35) lines, powered and matched,
to route data to core storage.
4. 1. 04 Multiplexor Address Switches
The address, where data are taken to or from, must be switched through the multi-
plexor address switches. These switches determine whether the address going to
core storage is from a data channel, the CPU, the multiplexor storage bus, or
is a forced address due to a channel trap. The switches also provide isolation between
the various inputs. The switches have three outputs, all of which are active simultan-
eously. Two of the outputs feed both banks of the data channels and terminate at the
location counter switches. The third output feeds the memory address register in core
storage.
4.2.00 DATA FLOW AND CONTROL
Data flow through the multiplexor and its associated control circuitry in the CPU
can best be described by examining the following paths:
CPU to core storage
Core storage to CPU
4.2.01 CPU to Core Storage
Data that flow from the CPU to core storage (Figure 4.1-3) are routed from the stor-
age register through the multiplexor storage bus OR ling circuits to the memory data
register. Data flow is controlled by gating at the output of the storage register. The
data are gated during an E cycle in which CPU control circuitry calls for store control.
The address at which the data are being stored is switched through the multiplexor
address switches. The CPU address register output is gated through these switches as
long as the B time trigger is not on. The address is sampled at the memory address
register at a given time.
The data flow from the multiplexor to core storage on 36 data lines. At core storage,
the data must be set to either 0-35 or 36-71 of the memory data register. The address
set to the memory address register specifies which half of the memory data register
is set.
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