Optional Boundary Scan Instructions; Fastflash Reconfiguration Instructions - Xilinx EZTag User Manual

Introduction
SAMPLE/PRELOAD. The SAMPLE/PRELOAD instruction allows a
snapshot of the normal operation of a components to be taken and
examined. It also allows data values to be loaded onto the latched
parallel outputs of the boundary scan shift register prior to the selec-
tion of other boundary-scan test instructions.
EXTEST. The EXTEST instruction allows testing of off-chip circuitry
and board level interconnections.

Optional Boundary Scan Instructions

INTEST. The INTEST instruction allows testing of the on-chip system
logic while the components are already on the board.
HIGHZ. The HIGHZ instruction forces all drivers into high imped-
ance states.
IDCODE. The IDCODE instruction allows blind interrogation of the
components assembled onto a printed circuit board to determine
what components exist in a product.
USERCODE. The USERCODE instruction allows a user-program-
mable identification code to be shifted out for examination. This
allows the programmed function of the component to be determined.
FastFLASH Reconfiguration Instructions
ISPEN. The ISPEN instruction activates the FastFLASH part for in-
system programming.
FPGM. The FPGM instruction is used to program the fuse locations at
a specified address.
FERASE. The FERASE instruction is used to perform an erase of a
block of fuse locations.
FVFY. The FVFY instruction is used to read the programming of the
fuse locations at a specified address.
ISPLD. The ISPLD instruction loads the programmed values into the
device memory. It then activates the device to operate according to
the programmed values.
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