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c
o
o
Condition Code 4-Attention
This code is reported when a keyboard entry or device going
Ready is detected.
Along with the interrupt condition code, the attachment
also transfers an interrupt ID word which provides
additional information on interrupting conditions.
Interrupt Identification Word
Acceptance of an I/O interrupt causes the attachment to
place an ID word in Register 7 (R7) of the interrupted
level. For condition code 2, the Interrupt ID word consists
of the Interrupt Status Byte (ISB) and the address of the
interrupting device. For condition code 4, the Interrupt
ID word consists of the Interrupt Information Byte (lIB)
and the address of the interrupting device. The first byte
will be zero for all other condition codes.
Interrupt ID word
\
IX/BX
I
Device address
\
.
X X X X X X.O X X X X X X X
o
7 8
15
Interrupt Information Byte
The 4979 uses an Interrupt Information Byte (ISB). This
byte is associated with an Attention Interrupt (CC-4),
caused by certain keyboard keys, or whenever the transition
from a device Not-Ready to a device Ready status is
detected.
lIB Keyboard Format
0-3
4
5-7
Not used-returned as zero
Ready Status detected
Keyboard Code Bits
o
through 3 of the keyboard bits are not used but are always
returned as O. Bits 5, 6 and 7 are the code bits for the keyboard,
entered by the 4979 during a keyboard interrupt. These bits
represent the interrupt key that was activated by the operator,
either ENTER, A TIN or one of the PROGRAM FUNCTION keys.
Bits 5 6 7
000
001
010
o
1 1
100
1 0 1
1 1 0
1 1 1
Enter
Attn
PF1 Lower
PF4 Upper
PF2 Lower
PF5 Upper
PF3 Lower
PF6 Upper
Bit 4 Ready Status Detected
This bit is set ON whenever a Not-Ready to Ready transition
condition occurs.
As a result of an Attention Interrupt, the user's program can
examine the liB bits (0-7) to determine exactly which interrupt
key was entered by the local operator, or to detect the 4979
going to a Ready condition.
Interrupt Status Byte
The ISB stores accumulated status information.
The format of the ISB is:
O-Device Dependent Status Available
I-Delayed Command Reject
2-(Not Used)
3- DCB Specification Check
4- Storage Data Check
5- Invalid Storage Address
6-Protect Check
7-Interface Data Check
Bit 2 of the ISB is not supported and should always be returned as
zero.
Bit 0- Device Dependent Status Available
Set ON when:
the display reaches a boundary condition (EOF, EOL, EOS)
prior to the byte count reaching zero, and causes an early
termination to the operation, or a Start command is issued when
the 4979 is in a Not-Ready state or a Not-Ready is detected
during a Start operation.
It
is also set on when the DCB parameters of a Start command
are incorrectly specified.
The status (residual address cursor address, status bits,
DCB and operation checks) can be examined by issuing a Start
Cycle Steal Status command.
Bit I-Delayed Command Reject
Set ON when:
the display cannot execute a command it has received. Included
are all Write commands and any Start commands with modifiers
other than 0001,
11
01 or 1111.
Bit 3-DCB Specification Check
Set ON when:
the display receives any incorrect DCB parameters necessary to
perform the desired operation. The operation is terminated.
The cause of the DCB check can be determined by a Start
Cycle Steal Status command, provided the DCB check was not
the result of a Start Cycle Steal Status command.
Bit 4-Storage Data Check
Set ON during:
a cycle steal output operation to indicate an incorrect parity
from accessed storage. The operation is terminated and the
party error in processor storage is not corrected.
Bit 5-Invalid Storage Address
Set ON during:
cycle steal I/O operations whenever the processor storage address
presented by the attachment for data or DCB access exceeds
the storage size on the system. The attachment records the
status, and the operation is terminated. Condition Code 2 is
reported at interrupt accept time.
Programming Input/Output Operations
3-11
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