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EN 36
9.
TE3.1E CA
9.4.3
MSP3415G
AHVSS
5 V
5 V
DVSS
DVSS
RESETQ
(from Controller, see section 4.6.3.3.)
TP
1
52
NC
2
51
D_CTR_I/O_1
3
50
D_CTR_I/O_0
4
49
ADR_SEL
5
48
STANDBYQ
6
47
I2C_CL
7
46
I2C_DA
8
45
I2S_CL
9
44
I2S_WS
10
43
I2S_DA_OUT
11
42
I2S_DA_IN1
12
41
ADR_DA
13
40
ADR_WS
14
39
ADR_CL
15
38
DVSUP
16
37
DVSS
17
36
I2S_DA_IN2
18
35
NC
19
34
RESETQ
20
33
NC
21
32
NC
22
31
VERF2
23
30
DACM_R
24
29
DACM_L
25
28
NC
26
27
Circuit Description and Abbreviation List
Signal GND
C s. section 4.6.2.
10
100
µF
SIF 1 IN
-
nF
Tuner
+
18.432
3.3
100
MHz
µF
nF
+
56 pF
56 pF
MONO_IN
330 nF
SC1_IN_L
330 nF
SC1_IN_R
330 nF
ASG
SC2_IN_L
330 nF
SC2_IN_R
330 nF
MSP 34x5G
STANDBYQ
ADR_SEL
I2C_DA
I2C_CL
ADR_WS
ADR_CL
ADR_DA
I2S_WS
I2S_CL
I2S_DA_IN1
I2S_DA_IN2
I2S_DA_OUT
220
470
470
pF
pF
pF
470
1.5
1.5
pF
nF
nF
1.5
10
10
µF
µF
nF
10
µF
5 V
5 V
8 V
(5 V)
XTAL_OUT
XTAL_IN
Sound IF1
TESTEN
NC
ANA_IN−
2
I
S1
ANA_IN1+
2
I
S2
AVSUP
AVSS
SCART1
MONO_IN
VREFTOP
SCART2
SC1_IN_R
SC1_IN_L
MONO
SC2_IN_R
SC2_IN_L
NC
NC
AGNDC
AHVSS
CAPL_M
AHVSUP
NC
SC1_OUT_L
SC1_OUT_R
VREF1
NC
52-pin PSDIP package
NC
Figure 9-3 Internal block diagram and pin configuration
8 V (5 V)
100 p
56 p
ANA_IN1+
Alternative circuit for
+
1 kΩ
SIF-in for more
10 µF
attenuation of video
components:
1 µF
DACM_L
1 µF
Loudspeaker
1 nF
DACM_R
1 nF
100Ω
22 µF
SC1_OUT_L
+
100Ω
22 µF
SC1_OUT_R
+
D_CTR_I/O_0
D_CTR_I/O_1
TESTEN
AHVSS
De-
Pre-
ADC
processing
modulator
Prescale
SCART
DSP
Input
ADC
Prescale
Select
Loud-
speaker
Loud-
DAC
Sound
speaker
Processing
2
I
S
DAC
DAC
SCART
Output
SCART1
Select
SCART2
F_15850_029.eps
20050824
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