Yamaha Disklavier Silent Mark III Service Manual page 27

TMS320VC5402 (XW685A00) DSP (Digital Signal Processor)
PIN
NAME I/O
No.
1 NC
2 NC
3 Vss
4 DVDD Power supply 1.8V
5 A10 O Address bus
6 HD7
I/O Parallel bidirectional data bus.
7 A11 O
8 A12 O
9 A13 O Address bus
10 A14 O
11 A15 O
12 NC
13 HAS I Address strobe.
14 Vss Ground
15 NC
16 CVDD Power supply 3.3V
17 HCS I Chip Select.
18 HR/W I Read/write.
19 READY I Data ready.
20 PS O
21 DS O Data, program, and I/O space select signals.
22 IS O
23 R/W O Read/write signal.
24 MSTRB O Memory strobe signal.
25 IOSTRB O I/O strobe signal.
26 MSC O Microstate complete.
27 XF O External flog output (latched software-programmable signal).
28 HOLDA O Hold acknawledge.
29 IAQ O Instraction acquisition signal.
30 HOLD I
31 BIO I Branch control.
32 MP/MC I Microprocessor/microcomputer mode select.
33 DVDD Power supply 1.8V
34 Vss Ground
35 NC
36 NC
37 NC
38 NC
39 HCNTL0 I Control.
40 Vss Ground
41 BCLKR0 I/O Receive clock input.
42 BCLKR1 I/O Receive clock input.
43 BFSR0 I/O Frome synchronization pulse for receive input.
44 BFSR1 I/O Frome synchronization pulse for receive input.
45 BDR0 I Serial deta receive input
46 HCNTL1 I Control.
47 BDR1 I Serial deta receive input
48 BCLKX0 I/O Transmit clock.
49 BCLKX1 I/O Transmit clock.
50 Vss Ground
51 HINT/TOUT1 O Host interrupt/Timer 1 output.
52 CVDD Power supply 3.3V
53 BFSX0 I/O Frome synchronization pulse for transmitinput/output.
54 BFSX1 I/O Frome synchronization pulse for transmitinput/output.
55 HRDY O Ready.
56 DVDD Power supply 1.8V
57 Vss Ground
58 HD0 I/O Parallel bidirectional data bus.
59 BDX0 O Signal data transmit output.
60 BDX1 O Signal data transmit output.
61 IACK O Interrupt acknowledge signal.
62 HBIL I Byte identification.
63 NMI I Nonmaskable interrupt.
64 INT0 I
65 INT1 I
Interrupt acknowledge signal.
66 INT2 I
67 INT3 I
68
CVDD Power supply 3.3V
69 HD1 I/O Parallel bidirectional data bus.
70 Vss Ground
71 NC
72 NC
FUNCTION
PIN
NAME I/O
No.
73 NC
74 NC
75 DVDD Power supply 1.8V
76 Vss Ground
77 CLKMD1 I
I Clock mode select signals.
78 CLKMD2
79 CLKMD3 I
80 NC
81 HD2 I/O Parallel bidirectional data bus.
82 TOUT0 O Timer 0 output.
83 EMU0 I/O Emulator 0 pin.
84 EMU1/OFF I/O Emulator 1 pin/disable outputs.
85 TDO O Testdata output
86 TDI I Test data input pin with interral pullup device.
87 TRST I Test reset.
88 TCK I Test clock.
89 TMS I Test mode output
90 NC
91 CVDD Power supply 3.3V
92 HPIENA I HPI module select.
93 Vss Ground
94 CLKOUT O Master clock output signal.
95 HD3 I/O Parallel bidirectional data bus.
96 X1 O Output pin from the internal oscillator for the crystal.
97 X2/CLKIN I Oscillator input. This is the input to the on-chip oscillator.
98 RS I Reset.
99 D0 I/O
100 D1 I/O
101 D2 I/O
Data bus
102 D3 I/O
103 D4 I/O
104 D5 I/O
105 A16 O Address bus
106 Vss Ground
107 A17 O
108 A18 O Address bus
A19 O
109
110 NC
111 Vss Ground
112 DVDD Power supply 1.8V
113 D6 I/O
114 D7 I/O
115 D8 I/O
116 D9 I/O
117 D10 I/O
118 D11 I/O
Data bus
119 D12 I/O
120 HD4 I/O
121 D13 I/O
122 D14 I/O
123 D15 I/O
124 HD5 I/O Parallel bidirectional data bus.
125 CVDD Power supply 1.8V
126 NC
127 HDS1 I Data strobe.
128 Vss Ground
129 HDS2 I Data strobe.
130 DVDD Power supply 3.3V
131 A0 O
132 A1 O
Address bus
133 A2 O
134 A3 O
135 HD6 I/O Parallel bidirectional data bus.
136 A4 O
137 A5 O
138 A6 O
Address bus
139 A7 O
O
140 A8
141 A9 O
142 CVDD Power supply 1.8V
143 NC
144 NC
DU1A
DSP: IC001
FUNCTION
(LSB)
(MSB)
(MSB)
(LSB)
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