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TERMINAL
NAME
PIN
CPVDD
1
CAPP
2
CPGND
3
CAPM
4
VNEG
5
OUTL
6
OUTR
7
AVDD
8
AGND
9
VCOM
10
MOSI
11
MC
12
GPIO5
13
GPIO4
14
GPIO3
15
GPIO2
16
MODE1
17
MS
18
(MODE2)
GPIO6
19
SCK
20
BCK
21
DIN
22
LRCK
23
MISO
24
(GPIO1)
XSMT
25
LDOO
26
DGND
27
DVDD
28
(1) Failsafe LVCMOS Schmitt trigger input.
/ I
O
-
Charge pump power supply, 3.3V
O
Charge pump flying capacitor terminal for positive rail
-
Charge pump ground
O
Charge pump flying capacitor terminal for negative rail
O
Negative charge pump rail terminal for decoupling, -3.3V
O
Analog output from DAC left channel
O
Analog output from DAC right channel
-
Analog power supply, 3.3 V
-
Analog ground
O
VCOM output by register setting of VCOM mode is optional, default setting is VREF mode
When VREF mode (default), this pin ties to GND
When VCOM mode, decupling capacitor to GND is required
(1)
I
Input data for SPI
(1)
I
Input clock for SPI
I/O
General purpose digital input and output port
I/O
General purpose digital input and output port
I/O
General purpose digital input and output port
I/O
General purpose digital input and output port
I
Mode control selection pin
MODE1=Low, MODE2=Low : Hardwired mode
MODE1=Low, MODE2=High : I2C mode
I
MODE1=High : SPI mode, MODE2 pin changes MS pin which is chip select for SPI
I/O
General purpose digital input and output port
(1)
I
System clock input
I
Audio data bit clock input
(1)
I
Audio data input
I
Audio data word clock input
I/O
Primary output data for SPI readback
Secondary general purpose digital input and output port controlled by register
(1)
I
Soft mute control
: Soft mute (Low) / soft un-mute (High)
-
Internal logic supply rail terminal for decoupling, 1.8V
-
Digital ground
-
Digital power supply, 3.3V or 1.8V
D
E
S
C
R
P I
I T
O
N
(1)
(1)
(1)
86
S
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