Sony STR-DN1070 Service Manual page 98

STR-DN1070
MB-1512 BOARD (11/16) IC3002 MB9BF128TAPMC-GE2 (SYSTEM CONTROLLER)
Pin No. Pin Name
1 VCC
2 RSTN_STATUS
3 NC
4 NC
5 NC
6 NC
7 DAC_DZF
8 TEST1/SWOUT_HPD
9 TEST2
TEST3/PCONT_
10
S2RAM
11 TEST4
12 TEST5
13 SUSPEND_INT
14 WLAN_RST
15 WIFI_PCONT
16 NC
17 SWSEL_A
18 SWSEL_B
19 CEC_IN_OUT
20 E2P_SDA
21 E2P_SCL
22 HDMI_CECIN
23 HDMI_CECOUT
24 CEC_PCONT
25 TEST_6
26 TEST_7
27 VSS
28 MTK_MUTE
29 BD_SCL(IF_SCK)
30 BD_SDI(IF_SDO)
31 BD_SDO(IF_SDI)
32 BD_CS(XIF_CS)
33 WOL_WLAN(WOL_INT)
BD_IF_START
34
(START_BIT)
35 BD_REQ(SYS_REQ)
BD_RESET
36
(CPU_XRST)
JIG_MODE1
37
(EXT_JIG_MODE1)
38 OPWRSB
39 UPG_STATUS
PCONT_WOL_
40
STANDBY
41 NAND_RESET
42 MTK_ZONE2_MUTE
43 MTK_ZONE2_RST
44 VSS
45 VCC
46 SIRCS_IN
47 HP_DET
48 NC
49 FL_ENABLE
50 FL_BK
51 FL_LAT
98
I/O
- Power supply pin (+3.3V)
O DAC RSTN Bit output to MT8506
- Not used
- Not used
- Not used
- Not used
I DAC Zero Data input detection
O Test pin output for Designer debugging.
O Test Pad 2 (for designer evaluation only)
O Test pin output for Designer debugging.
O Test Pad 4 (for designer evaluation only)
O Test Pad 5 (for designer evaluation only)
O Interrupt output pin to wake up STR
O Reset signal output to wireless module.
I Power control detection input from wireless module
- Not used
O HDMI Switcher 5V Power Select
O HDMI Switcher 5V Power Select
I/O CEC Input/Output Peripheral
I/O Two-way data bus with the EEPROM
O Serial data transfer clock signal output to the EEPROM
I CEC serial data input from the HDMI connector
O CEC serial data output to the HDMI connector
O Control the CEC relay at HDMI out terminal.
O Test Pad 6 (for designer evaluation only)
O Test Pad 7 (for designer evaluation only)
- Ground terminal
I Muting Detection input from MT8506
I Serial data transfer clock signal input from MT8506
O Serial data output to MT8506
I Serial data input from MT8506
O Chip select signal output to MT8506
I WOL (wake-on-LAN) wake-up signal input from MT8506 "H":wake-up
O Ready signal output to MT8506 "H":ready
I Request signal input from MT8506 "H": request
O Reset signal output to MT8506 "L": reset
This port is Jig mode selection signal OUTPUT to MT8506.
I/O
(Normal case this port is input. Output LOW when USB update start by FLD.)
I Power control signal input from the BD decoder
I UPG signal input from MT8506
O Wake On Lan Power Control
O Reset signal output to the NAND fl ash "L": reset
O MTK ZONE2 DAC MUTE
O MTK ZONE2 DAC RESET
- Ground terminal
- Power supply pin (+3.3V)
I SIRCS signal input
I Headphone Detection signal input
- Not used
O Enable control for FL DISPLAY DRIVER IC
O Blanking period signal output to the fl uorescent indicator tube
O Latch signal output for FL DISPLAY DRIVER IC
Description
(Not Used)
(Not Used)