Schematic Diagrams - Yamaha A-S701 Service Manual

A B C

■ SCHEMATIC DIAGRAMS

1
DIGITAL
+ 5 M T R
2
4.98
C B 3 0 1
+ 5 M T R
1
V R G
2
M G
3
F W _ S D O
0.0018
4
D I R _ N _ I N T
0.0330
5
D I R _ N _ C S
2.99
6
D I R _ M O S I
0.54
Page 54 K2 7
3
F W _ W C K
to FUNCTION (1)_CB517
8
D I R _ S C L K
9
U S B _ O C P R T
1 0
D I R _ M I S O
1 1
D I G I T A L _ P O N
1 2
D I R _ N _ R S T
1 3
N C
1 4
1 4 F M N - S M T - A - T F (
4
D G N D
+ 5 V
5
I v o l = 1 0 A M A X
J S R 2 1 6 5
4.98
O P T I C A L C 3 0 1
OPICAL
0 . 1 / 1 6 R 3 0 1
1 0 0 0.0001
D G N D
DIGITAL R 3 3 8
2.48
6 8 0
C 3 0 7
P J 3 0 1 n o _ u s e
C 3 0 8
0.0000
COAXIAL
2.466
C O A X I A L 0 . 1 / 1 6
6
M S P - 2 5 1 V - 1 4 - G I L
+ 5 V
4.98
I C 3 0 7 V +
8
3 5 C 3 5 0
0 . 1 / 1 6
4
V -
1.75
7
+ 7 I
W 3 0 1
+ 7 I
Page 57 C6
1
to OPERATION (8)_CB21 I G N D
2
S C N - X H
8
D G N D
Details of colored lines
★ All voltages are measured with a 10M Ω /V DC electronic voltmeter.
★ Components having special characteristics are marked ⚠ and must be replaced
Red / full line: Power supply (+)
with parts having specifications equal to those originally installed.
Red /dashed line: Power supply (-)
★ Schematic diagram is subject to change without notice.
Orange: Signal detect
Yellow: Clock
Green: Protection detect
Brown: Reset signal
Blue: Panel key input
9
N O T I C E
( m o d e l ) R E S I S T O R
J J A P A N
R E M A R K S P A R T S N A M E
U U . S . A
N O M A R K C A R B O N F I L M R E S I S T O R ( P = 5 )
C C A N A D A
C A R B O N F I L M R E S I S T O R ( P = 1 0 )
R G E N E R A L
M E T A L O X I D E F I L M R E S I S T O R
T C H I N A
M E T A L F I L M R E S I S T O R
K K O R E A
M E T A L P L A T E R E S I S T O R
A A U S T R A L I A
F I R E P R O O F C A R B O N F I L M R E S I S T O R
B B R I T I S H
C E M E N T M O L D E D R E S I S T O R
G S T A N D A R D
S E M I V A R I A B L E R E S I S T O R
10 L S I N G A P O R E
C H I P R E S I S T O R
E S O U T H E U R O P E
V T A I W A N
F R U S S I A N
P L A T I N A M E R I C A
S B R A Z I L
H T H A I
D E F
R 3 0 3
0.0
0.0
4.8
0.0
R 3 0 5
0.0019 2 2 X 4
0.0
4.62
4.94
4.98 4.98
3.93
4.92
R 3 0 2
4.94 2 2 X 4 4.93
2 2 R 3 0 4 3 . 3 V - > 5 V
4.96
2 2
4.96
+ 5 V
4.98
C 3 5 1
I C 3 0 8 0 . 1 / 1 6
V + D G N D
1 4
4
6
5
9
8
1 0
1 2
1 1
1 3
1
3
2
7
T C 7 4 V H C T 0 8 A F T ( E V -
D G N D
DIGITAL IN
+ 3 . 3 D
R 3 3 9
+ 3 . 3 D
1.99
3.29
4 . 7 K
I C 3 0 7 I C 3 0 7 + 3 . 3 D
1 7 6 2 R 3 4 2
0.36
3 3
T C 7 W H U 0 4 F K
3.29
R 3 4 0
3.29 3.299
1 8 K
R 3 4 1
n o _ u s e 0.39
3.29
3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5
R X I N 0 M D I / S D A
3 7 3.94 2 4
G N D R X M D O / A D R 0
3 8 2 3
X T I D V D D C 3 2 0
3 9 2 2
0 . 1 / 1 0 ( B J )
C 3 1 5 C 3 1 7 X T O D G N D
4 0 2 1
1.75
1 0 / 6 . 3
A G N D S C K O
I C 3 0 1 1.4976
4 1 2 0
0 . 1 / 1 6
V C C B C K
1.6192
4 2 P C M 9 2 1 1 P T R 1 9
C 3 0 6
X L 3 0 1
0.00 F I L T L R C K
4 3 1 8 1.6487
4 3
1.75
4 7 0 0 P / 2 5 ( B ) V C O M D O U T
0.0012
4 4 1 7
C 3 0 5
1 2 R 3 1 1 A G N D A D M P O 1
2 4 . 5 7 6 M H Z 4 5 1 6
0.00 6 8 0
0 . 0 6 8 / 2 5 V C C A D M P O 0
4 6 1 5
V I N L M P I O _ B 3
4 7 1 4
V I N R M P I O _ B 2
4 8 1 3
1 2 3 4 5 6 7 8 9 1 0 1 1 1 2
C 3 1 8
n o _ u s e
D G N D
I d d = 5 5
+ 3 . 3 D
D G N D
R 3 1 2
1 0 K
C A P A C I T O R
R E M A R K S P A R T S N A M E
V
N O M A R K E L E C T R O L Y T I C C A P A C I T O R
T A N T A L U M C A P A C I T O R
N O M A R K C E R A M I C C A P A C I T O R
C E R A M I C T U B U L A R C A P A C I T O R
P O L Y E S T E R F I L M C A P A C I T O R
P O L Y S T Y R E N E F I L M C A P A C I T O R
M I C A C A P A C I T O R
P P O L Y P R O P Y L E N E F I L M C A P A C I T O R
S E M I C O N D U C T I V E C E R A M I C C A P A C I T O R
P O L Y P H E N Y L E N E S U L F I D E F I L M
S
C A P A C I T O R
G H
I C 3 0 9
T P S 2 0 5 1 C D B V R
I N O U T
G N D
+ 5 V
E N F L T
U B A - 4 R - D 1 4 C - 2
C B 3 0 2
P A D 1
6
4.98 I N O U T 4.98 V B u s
1
G N D I L I M N . C
2
E N F L A G N . C
3
G N D
n o _ u s e
4
5
- -
m i n 0 . 5 5 A
D G N D
H S 3 0 1
@ p a r t N
B P U E 1 6 - 2 5 / H 1 7
5 V / 8 0 0 m A
N J M 2 3 8 8 F 0 5
+ 5 V + 5 M T R 4
Q 3 0 1
R A L 0 3 5 P 0 1 4.98
4.98
6 5 4
1 2 3
0.00
Q 3 0 2
D T C 1 1 4 E K A
+ 3 . 3 A
3.2994
+ 3 . 3 D
DAC
R 3 1 9 I d d = 1 3 A M A X
1 0 K I c c = 3 2 A M A X
D A C
C 3 2 4
D G N D 0.0001
s 8
C 3 2 1 D V D D C P V D D
D G N D C A P P
1 0 / 6 . 3
L D O O C P G N D
R 3 1 6
X S M T C A P M
3 3 3.25
A s i d e R 3 2 6 F M T V N E G
4 . 7 K 0.00
D I R _ W C K L R C K O U T L
R 3 2 0
D I R _ M C K
1.5337
D I R _ S D O D I N O U T R
1 0 0
R 3 1 7 D I R _ B C K
1.6211 D I R _ B C K B C K A V D D
3 3 R 3 2 1
D I R _ W C K
1.6488 D I R _ M C K S C K A G N D
3 3
R 3 1 8 D I R _ S D O
0.0012 R 3 2 7
F L T D E M P
3 3
1 K 0.000
3.29
R 3 4 7
0.0013
C 3 2 8
3 3 R 3 2 8
0.0001 2 . 2
s 9
0.03
D G N D
A M A X
IC309 : TPS2051CDBVR
Power-Distribution Switch
Current
Sense
IN
Charge
Pump
EN or
EN
UVLO
GND
IC306 : RP170H331B-T1-FE IC306 : RP170H331B-T1-FE
IC305 : RP130Q331D-TR-F
Voltage regulator Voltage regulator
Voltage regulator
V V
V DD 5 1 OUT
DD 4 3 OUT
Vref
Vref Current Limit
Thermal Shutdown
Current Limit
CE 3 2 GND
CE 1 2 GND
Pin No. Symbol Description
1 CE Chip Enable ("H" Active) Pin No. Symbol Description
1
2 GND Ground Pin VOUT Output Pin
2 GND Ground Pin
3 V OUT Output Pin
3 CE Chip Enable Pin
4 V DD Input Pin
4 NC No Connection
5 VDD Input Pin
I J K
D e s t i n a t i o n P a r t L i s t
+ - - - - - - - - + - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - +
| s x x | L O C A T I O N | U R A L | B |
+ - - - - - - - - + - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - +
| s 8 | C 3 2 4 | U R 2 3 7 1 0 | U U 2 3 7 1 0 | U U 2 3 7 1 0
| | | 1 0 / 1 6 | 1 0 / 1 6 |
+ - - - - - - - - + - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - +
| s 9 | C 3 2 8 | Z D 5 2 0 0 0 | W E 1 0 2 9 0 | W E 1 0 2 9 0
| | | 0 . 0 1 / 1 0 0 | 0 . 0 1 / 1 0 0 | 0 . 0 1 / 1 0 0
+ - - - - - - - - + - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - +
| s 1 0 | C 3 3 1 | U R 2 3 7 4 7 | U R 0 3 7 4 7 | U R 0 3 7 4 7
| | | 4 7 / 1 6 | 4 7 / 1 6 |
+ - - - - - - - - + - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - +
| s 1 1 | C 3 3 3 | U R 2 3 7 1 0 | U U 2 3 7 1 0 | U U 2 3 7 1 0
| | | 1 0 / 1 6 | 1 0 / 1 6 |
+ - - - - - - - - + - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - +
DC OUT | s 1 2 | C 3 3 5 | Z D 5 1 9 2 0 | W E 1 0 2 1 0 | W E 1 0 2 1 0
| | C 3 3 6 | 2 2 0 0 P / 1 0 0 | 2 2 0 0 P / 1 0 0 | 2 2 0 0 P / 1 0 0
+ - - - - - - - - + - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - +
| s 1 3 | C 3 3 8 | U R 2 3 8 1 0 | U R 0 3 8 1 0 | U R 0 3 8 1 0
| | | 1 0 0 / 1 6 | 1 0 0 / 1 6 | 1 0 0 / 1 6
D C O U T f o r B T
+ - - - - - - - - + - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - +
| s 1 4 | C 3 4 2 | U R 2 4 8 2 2 | U R 0 4 8 2 2 | U R 0 4 8 2 2
5 V / 5 0 0 m A
| | | 2 2 0 / 2 5 | 2 2 0 / 2 5 | 2 2 0 / 2 5
+ - - - - - - - - + - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - +
| s 1 6 | C B 3 0 3 | X | L B 9 1 9 0 4 | L B 9 1 9 0 4
| | | | X H L |
+ - - - - - - - - + - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - +
| s 1 7 | C 3 6 1 | U R 2 3 7 1 0 | U U 2 3 7 1 0 | U U 2 3 7 1 0
| | | 1 0 / 1 6 | 1 0 / 1 6 |
+ - - - - - - - - + - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - +
I C 3 0 4
3 . 3 D / 7 0 m A 3 . 3 A / 3 0 m A
+ 7 I
3 2 1 S T 3 0 1
+ 5 V + 3 . 3 D + 7 V + 3 . 3 A
I C 3 0 6
R 3 3 3
Y F 0 1 6 A 0
Y C 2 8 8 A 0
n o _ u s e
R P 1 7 0 H 3 3 1 B - T 1 - F
R P 1 3 0 Q 3 3 1 D - T R - F
10.0 V D D V O U T
4.98 3.29 7.21 3.29
G N D
D 3 0 2
D G N D
N C C E
4 3
n o _ u s e
I C 3 0 5
1 2
C 3 5 5
4.92
0 . 1 / 1 6
D G N D A G N D
D G N D
C 3 3 3
0.0001 + 7 V - 7 V
3.29
s 1 1
1.66
P H L
- 7 V
-7.125
1
2 . 2 / 1 0
+ 7 V
C 3 2 9 7.204
2
-1.61
C 3 3 4 A G N D Page 54 D2
-3.27
3
2 . 2 / 1 0 R 3 3 0 to FUNCTION (2)_W403
D A C _ L
0.0005
4
R 3 2 9 1 P 4 7 0 J 3 0 3
A G N D
5
1 P 4 7 0 0 D A C _ R
0.0005
6
C B 3 0 4
s 1 2
R 3 3 1
C 3 3 1 0.0012
4 . 7 K
s 1 0
C B 3 0 3
Page 54 C2
+ 3 . 3 A
to FUNCTION (2)_W404
A G N D
s 1 6
IC301: PCM9211PTR
216-kHz digital audio interface transceiver (DIX) with stereo ADC and routing
DIGITAL (1)
RXIN0
RXIN1
RXIN2
RXIN3
RXIN4/ASCKIO
RXIN5/ABCKIO
RXIN6/ALRCKIO
CS OUT
RXIN7/ADIN0
(Disabled+
Current
UVLO) MPIO_A0
Limit
MPIO_A1
MPIO_A2
Driver MPIO_A3
FLT
9-ms
OTSD
Deglitch
Thermal
Sense VINL
VINR
VCOM
IC303 : PCM5101APWR
MPIO_C0
106 dB audio selector DAC with 32-bit, 384 kHz PCM interface
MPIO_C1
MPIO_C2
Current
MPIO_C3
Segment 6
OUT L
DIN (I 2 S) 14
DAC
Current
Segment 7 OUT R
XTO
DAC
Zero
Data
Advanced Mute Control
Detector
MC/SCL
MDI/SDA
Clock Halt
MDO/ADR0
Detection
MS/ADR1
1 CPVDD (3.3V)
LRCK 15
8
Power AVDD (3.3V)
BCK 13
PLL Clock 20
Supply DVDD (3.3V)
RST
SCK 12 UVP/Reset POR Ch. Pump
GND
MODE
3,9,19
5 4 2
L M N
A-S701
G |
|
1 0 / 1 6 |
|
|
|
4 7 / 1 6 |
|
1 0 / 1 6 |
|
|
|
|
|
|
|
X H L |
|
1 0 / 1 6 |
S T 3 0 2 S T 3 0 3 C 3 4 6
R 3 3 5
P
n o _ u s e n o _ u s e
M G D G N D
D 3 0 4
n o _ u s e
D 3 0 3
n o _ u s e
C 3 5 6
R 3 4 6
n o _ u s e n o _ u s e
A G N D D G N D
F G
IC304: NJM4580E
Dual operational amplifier
V+
8
2, 6 1, 7 OUTPUT
–INPUT
+INPUT
3, 5
V–
4
FILT
43
AUXIN0
AUTO
RXIN7
RXIN0 DIR DIR
37 20 SCKO
RXIN1 ADC DOUT
35 PLL MAIN 19 BCK
OUTPUT
RXIN2 AUXIN0
33 PORT 18 LRCK
SCKO/BCK/LRCK
RXIN3 AUXIN1
32 17 DOUT
RXIN4 Lock:DIR AUXIN2
31
Unlock:ADC
RXIN5
30 Clock/Data
Recovery
RXIN6
29
RXIN7 AUTO
28
DIR
Lock
RXIN8 ADC
3
Detection
RXIN9 DIT
4 AUXIN0
MPIO_A
SELECTOR RXIN10 AUXIN1
5
RXIN11 RECOUT0 AUXIN2
6
DITOUT RECOUT1
RECOUT0
15 MPO0
RECOUT1 MPO0/1
SELECTOR
ADC 16 MPO1
DITOUT
47
ADC Mode
ADC
Control
48
44 Com. Supply
AUTO
ADC Standalone DIR
7 11 MPIO_B0
ADC
8 12 MPIO_B1
MPIO_C AUXOUT MPIO_B
SELECTOR AUXIN0 SELECTOR
9 13 MPIO_B2
AUXIN1 AUXIN2
AUXIN1
10 14 MPIO_B3
AUXIN2
ADC Clock
(SCK/BCK/LRCK)
Divider
XTI 39
OSC
40
XMCKO SBCK/SLRCK
Secondary SCK/LRCK
(To MPIO_A and MPO0/1) (To MPIO_A)
XMCKO Divider
Divider
Selector
REGISTER EXTRA DIR FUNCTIONS
25 1 ERROR/INT0
SPI/I 2 C
DIR DIR
24 INTERFACE Function DIR CS ERROR DETECTION NPCM/INT1
PC PD 2
Control (48-bit) and IS Calculator
Non PCM DETECTION
23
Is Calculator
MPIO_A
26 Flags
GPIO/GPO DIT CS DIR All Port
Data (48-bit) Interrupt IS Calculator DTS-CD/LD Detection MPIO_B
Validity Flag MPIO_C
User Data
MPO0
POWER SUPPLY Channel Status Data
34 Reset and BFRAME Detection MPO1
ADC DIR DIR
Mode ALL Interrupt System
27
Set ANALOG ANALOG ANALOG
46 45 42 41 36 38 22 21
V C C A D A G N D A D V C C A G N D VDDRX GNDRX D V D D D G N D
53