Main Unit; Cpu Board (Mpr) - Panasonic KX-NS500AG Service Manual

4.2.

Main Unit

The Main Unit is constructed by CPU Board (MPR) and Mother Board. The block diagram and operation of each card are
described here.
4.2.1.

CPU Board (MPR)

Fig.2 shows detail block diagram of CPU Board (MPR) , and each function of CPU Board (MPR) is described in Table.4.
L1 32K/32K
L2 256K w/ECC
176K ROM
DC/DC(+3.3V,+1.8V,+1.1V)
Fig.2 CPU Board (MPR) Block Diagram
Table.4 CPU Board (MPR) Function Description
Device/Function Block
CPU
DDR3
NAND Flash
SRAM
FPGA
USB
L2SW/LAN(RJ45)
SD Card
RTC
ARM
DDR
Cortex- A8
512MB
Interface
600MHz
w/SED
Crypto
64K RAM 64K RAM
NAND
etc.
I2C
Interrupt
SD-I/F SD- Card
SD
Connector
McASP
RMII
Ethernet
UART - I/F
UART
GPIO
USB - Host- I/F
USB
+5V
CPU controls exchange and monitoring functions of the whole NS500 system.
DDR3 is main memory of CPU Board (MPR). Operating system, application program and concerning data are
stored in this memory.
Program and system data are stored in this memory.
SRAM is backed up by battery, and system information is stored this non-volatilized memory.
FPGA provides basic PBX function such as time switch, tone generation and so on.
USB master port for maintenance.
LAN port is used for VoIP and Web-MC connection.
UM voice data are stored in this SD card.
RTC is battery backed up clock which maintains system clock of NS500 system.
LAN USB
RJ45 TypeA
DDR3
External bus
8bit 16bit 16bit
NAND
SRAM
FLASH
512KB
1GB
RTC
PHY
L2SW
PHY
PHY
AC_ALM, DC_ALM, System Reset, FPGA_REBOOT, DONE
EXP- M
Connector
Description
9
LED
8bit
ER,DR
Master
FPGA
TDM
+5V
+15V
+5V
DC/DC
+3.3V
+VBAT
KX-NS500AG