Page 1 Cat. No. W140-E1-04 SYSMAC C1000H/C2000H Programmable Controllers...
Page 2 C1000H/C2000H Programmable Controllers Operation Manual Revised May 2003...
Page 4 OMRON. No patent liability is assumed with respect to the use of the information contained herein. Moreover, because OMRON is constantly striving to improve its high-quality products, the information contained in this manual is subject to change without notice.
Page 6: Table Of Contents
............OMRON Product Terminology .
Page 7 SECTION 5 Instruction Set ........Notation .
Page 8 SECTION 8 Error Processing ....... . . Alarm Indicators ............Programmed Alarms and Error Messages .
Page 9 It also provides an overview of the process of programming and operating a PC and explains basic terminology used with OMRON PCs. Descriptions of peripheral devices used with the C1000H and C2000H and a table of other manuals available to use with this manual for special PC applications are also provided.
Page 10 WARNING Failure to read and understand the information provided in this manual may result in personal injury or death, damage to the product, or product failure. Please read each section in its entirety and be sure you understand the information provided in the section and related sections before attempting any of the procedures or operations given.
Page 11 It also provides an overview of the process of programming and operating a PC and ex- plains basic terminology used with OMRON PCs. Descriptions of peripheral devices used with the C1000H and C2000H, and a table of other manuals available to use with this manual for special PC applications, are also provided.
Page 12: Overview
The terminology used throughout this manual is somewhat different from re- lay terminology, but the concepts are the same. The following table shows the relationship between relay terms and the PC terms used for OMRON PCs. Relay term PC equivalent...
Page 13: Pc Terminology
PC Terminology Section 1-3 Actually there is not a total equivalence between these terms. The term con- dition is only used to describe ladder diagram programs in general and is specifically equivalent to one of certain set of basic instructions. The terms input and output are not used in programming per se, except in reference to I/O bits that are assigned to input and output signals coming into and leaving the PC.
Page 14: Omron Product Terminology
Appendix A Standard Models list products according to these groups. The term Unit is used to refer to all of the OMRON PC products. Al- though a Unit is any one of the building blocks that goes together to form a C1000H or C2000H PC, its meaning is generally, but not always, limited in context to refer to the Units that are mounted to a Rack.
Page 15: Peripheral Devices
The following peripheral devices can be used in programming, either to input/ debug/monitor the PC program or to interface the PC to external devices to output the program or memory area data. Model numbers for all devices listed below are provided in Appendix A Standard Models. OMRON product...
Page 16 A Host Link Unit is required to interface a computer running LSS to the PC. Factory Intelligent Terminal: The FIT is an OMRON computer with specially designed software that allows you to perform all of the operations that are available with the GPC or LSS.
Page 17: Available Manuals
Available Manuals Section 1-7 Available Manuals The following table lists other manuals that may be required to program and/ or operate the C1000H and C2000H. Operation Manuals and/or Operation Guides are also provided with individual Units and are required for wiring and other specifications.
Page 18: Hardware Considerations
SECTION 2 Hardware Considerations This section provides information on hardware aspects of the C1000H and C2000H that are relevant to programming and software operation. These include indicators on the CPU and Duplex Unit and basic PC configuration. This information is covered in detail in the C1000H/C2000H Installation Guide. Indicators .
Page 19: Indicators
Lights when an error is discovered in error diagnosis operations. PC operation will continue. OUT INHB Lights when the Output OFF bit, SR bit 25215, is turned ON. All outputs from the PC will be turned OFF. SYSMAC C2000H PROGRAMMABLE CONTROLLER POWER ALARM OUT INHB...
Page 20 Indicators Section 2-1 Duplex Unit Indicators Duplex Unit indicators are shown and described below. Refer to the C1000H/C2000H Installation Guide for details. Duplex operation is only avail- able on C2000H Units. Indicator Function DUPLEX RUN Lights when the Duplex Unit is operating normally. DUPLEX BUS Lights when an error has occurred in the Duplex Unit bus.
Page 21: Pc Configuration
PC Configuration Section 2-2 PC Configuration The basic PC configuration consists of either two or three types of Rack: a CPU Rack and Expansion I/O Racks for C2000H Simplex Systems and the C1000H, and a CPU Rack, a CPU I/O Rack, and Expansion I/O Racks for C2000H Duplex Systems.
Page 22 PC Configuration Section 2-2 C1000H System, or in C2000H Simplex or Duplex Systems, up to seven Ex- pansion I/O Racks can be connected in series to the CPU Rack or, in a C2000H Duplex System, to the CPU I/O Rack. Unit Mounting Position Only I/O Units and Special I/O Units can be mounted to Slave Racks.
Page 23: Memory Areas
SECTION 3 Memory Areas Various types of data are required to achieve effective and correct control. To facilitate managing this data, the PC is pro- vided with various memory areas for data, each of which performs a different function. The areas generally accessible by the user for use in programming are classified as data areas..
Page 24: Introduction
Data Area Structure Section 3-2 Introduction Details, including the name, acronym, range, and function of each area are summarized in the following table. All but the last three of these areas are data areas. Data and memory areas are normally referred to by their acro- nyms.
Page 25 Data Area Structure Section 3-2 An actual data location within any data area but the TC area is designated by its address. The address designates the bit or word within the area where the desired data is located. The TC area consists of TC numbers, each of which is used for a specific timer or counter defined in the program.
Page 26: Ir (Internal Relay)Area
IR Area Section 3-3 tains four digits, which are numbered from right to left. These digit numbers and the corresponding bit numbers for one word are shown below. Digit number Bit number Contents When referring to the entire word, the digit numbered 0 is called the right- most digit;...
Page 27 IR Area Section 3-3 words (work bits), which can be used in programming to manipulate data and control other bits. IR area work bits are reset when power is interrupted or PC operation is stopped. I/O words I/O bits Work words Work bits C1000H 000 through 063...
Page 28 IR Area Section 3-3 signed the next word(s) following the word(s) assigned to the previous Unit. If there are any empty slots, no words will be assigned. Words are only as- signed when a Unit is mounted; all empty slots are skipped. The number of I/O words allocated to each type of Unit is shown below.
Page 29 IR Area Section 3-3 der is illustrated below. Arrows indicate the order in which words are allo- cated to Units. Starting point C2000H CPU Rack C2000H Duplex CPU Rack I/O Control Unit Duplex Unit Empty slot (no words allocated) Starting point Expansion I/O Rack CPU I/O Rack I/O Control Unit...
Page 30 IR Area Section 3-3 the right of the Master. If 18 words we required by the Units on the Slave Racks, the first word allocated to the Unit to the right of the Master would be IR 35. I/O word allocations for other Remote I/O Units are not according to the mounting order of their Master.
Page 31: Sr (Special Relay) Area
SR Area Section 3-4 Table Change operation must be performed after the I/O Table Registration operation, otherwise all word reservations will be cancelled, and I/O Table Change will have to be repeated. SR (Special Relay) Area The SR area contains flags and control bits used for monitoring PC opera- tion, accessing clock pulses, and signalling errors.
Page 32: Link System Flags And Control Bits
SR Area Section 3-4 Word(s) Bit(s) Function 00 to 07 FAL number output area. Low Battery Flag Cycle Time Error Flag I/O Verification Error Flag Rack-mounting Host Link Unit Level 0 Error Flag Remote I/O Error Flag Normally ON Flag Normally OFF Flag First Cycle 1-minute clock pulse bit...
Page 33 SR Area Section 3-4 Bits 04 to 15 If the content of bits 12 through 15 is B, an error has occurred in a Remote I/O Master or Slave Unit, and the content of bits 08 through 11 will indicate the mounting order of the Master of the Remote I/O Subsystem involved.
Page 34 SR Area Section 3-4 Completion Name Meaning code Normal end Data transfer was completed successfully. Parameter error SEND(90)/RECV(98) instruction operands are not within specified ranges. Transmission impossible The System was reset during execution of the instruction or the destination node is not in the System. Destination not in System The destination node is not in the System.
Page 35 SR Area Section 3-4 SYSMAC NET Link Systems Level 0 Level 1 Bit numbers in header/data link table entry numbers in table body SW3-4 SW3-4 PC Error Flags PC Run Flags SR 238 SR 242 SR 247 SR 239 SR 243 SR 248 SR 240 SR 244...
Page 36: Data Retention Control Bit
SR Area Section 3-4 Multilevel PC Link Systems Flag type Bit no. SR 247 SR 248 SR 249 SR 250 Run flags Unit #8, Unit #0, Unit #8, Unit #0, level 1 level 1 level 0 level 0 Unit #9, Unit #1, Unit #9, Unit #1,...
Page 37: Output Off Bit
SR Area Section 3-4 3-4-3 Output OFF Bit SR bit 25215 is turned ON to turn OFF all outputs from the PC. The OUT INHB. indicator on the front panel of the CPU will light. When the Output OFF Bit is OFF, all output bits will be refreshed in the usual way. The status of the Output OFF bit is maintained for power interruptions or when PC operation is stopped.
Page 38: Step Flag
SR Area Section 3-4 These clock pulse bits are often used with counter instructions to create tim- ers. Refer to 5-11 Timer and Counter Instructions for an example of this. Pulse width 1 min 0.02 s 0.1 s 0.2 s 1.0 s 25400 25401...
Page 39: Ar (Auxiliary Relay) Area
AR Area Section 3-5 word that is non-existent. When the ER Flag is ON, the current instruction will not be executed. 3-4-13 Arithmetic Flags The following flags are used in data shifting, arithmetic calculation, and com- parison instructions. They are generally referred to only by their two-letter abbreviations.
Page 40 AR Area Section 3-5 AR Area Flags and Control Bits Word(s) Bit(s) Function 00 to 03 Data Link setting for operating level 0 of SYSMAC LINK System 05 to 07 Data Link setting for operating level 1 of SYSMAC LINK System 08 to 15 Not used.
Page 41: 3-5-1 Sysmac Link System Data Link Settings
AR Area Section 3-5 Word(s) Bit(s) Function 00 to 03 Leftmost digit of FALS-generating address (AR 25 contains the other four digits) 04 and 05 Not used and not accessible by user. Level 1 Network Parameter Flag Level 0 Network Parameter Flag 08 to 10 Not used and not accessible by user.
Page 42: Sysmac Link/Sysmac Net Link System Service Time
AR Area Section 3-5 These flags are refreshed every cycle while the SYSMAC LINK System is operating. The body of the following table show the node number assigned to each bit. If the bit is ON, the node is currently active. Level 0 Level 1 Bit (body of table shows node numbers)
Page 43: On-Line Removal Bits
AR Area Section 3-5 Name Function File Memory Unit Error Reset Bit AR 1900 Turned ON from program to reset AR 1903 through AR 1906. FM Data Transfer Flag AR 1901 ON while FM data is being transferred. FM Write/Read Flag AR 1902 ON during transfers to FM;...
Page 44: Dm (Data Memory) Area
DM Area Section 3-6 Change 1 operation from the Programming Console. (Refer to 7-6-3 Hex/ BCD Data Modification for details.) The Power-Off Counter is refreshed every time power is turned on. 3-5-8 Network Parameter Flags AR 2406 is ON when the actual setting of the network parameter for operat- ing level 1 of the SYSMAC LINK System differs from the setting at the FIT.
Page 45: Hr (Holding Relay) Area
TC Area Section 3-8 as LD, OUT, AND, and OR, nor can DM words be used with the SHIFT in- struction. The DM area retains status during power interruptions. Indirect Addressing Normally, when the content of a data area word is specified for an instruction, the instruction is performed directly on the content of that word.
Page 46: Lr (Link Relay) Area
TC Area Section 3-8 TIMW<13>, TMHW<15>, or CNTW<14>. No prefix is required when using a TC number as a definer in a timer or counter instruction. Once a TC number has been defined using one of these instructions, it can- not be redefined elsewhere in the program either using the same or a differ- ent instruction.
Page 47: Program Memory
TR Area Section 3-13 section. Refer to 5-7 Interlock and Interlock Clear – IL(02) and ILC(03) for details on interlocks. 3-10 Program Memory Program Memory is where the user program is stored. The amount of Pro- gram Memory available is either 8K,16K, 24K or 32K words, depending on the type of Memory Unit mounted to the CPU.
Page 48: Writing And Inputting The Program
SECTION 4 Writing and Inputting the Program This section explains the basic steps and concepts involved in writing a basic ladder diagram program, inputting the pro- gram into memory, and executing it. It introduces the instructions that are used to build the basic structure of the ladder diagram and control its execution.
Page 49: Basic Procedure
Instruction Terminology Section 4-2 Basic Procedure There are several basic steps involved in writing a program. Sheets that can be copied to aid in programming are provided in Appendix F I/O Assignment Sheets and Appendix G Program Coding Sheet. 1, 2, 3... 1. Obtain a list of all I/O devices and the I/O points that have been as- signed to them and prepare a table that shows the I/O bit allocated to each I/O device.
Page 50: Basic Ladder Diagrams
Basic Ladder Diagrams Section 4-3 Other terms used in describing instructions are introduced in Section 5 In- struction Set. Basic Ladder Diagrams A ladder diagram consists of one line running down the left side with lines branching off to the right. The line on the left is called the bus bar; the branching lines, instruction lines or rungs.
Page 51: Mnemonic Code
Basic Ladder Diagrams Section 4-3 something to happen when a bit is ON, and a normally closed condition when you want something to happen when a bit is OFF. 00000 Instruction is executed Instruction when IR bit 00000 is ON. Normally open condition 00000...
Page 52: Ladder Instructions
Basic Ladder Diagrams Section 4-3 Program Memory addresses start at 00000 and run until the capacity of Pro- gram Memory has been exhausted. The first word at each address defines the instruction. Any definers used by the instruction are also contained in the first word.
Page 53 Basic Ladder Diagrams Section 4-3 tion in the following examples and could be any of the right-hand instructions described later in this manual. 00000 Address Instruction Operands A LOAD instruction. 00000 00000 00001 Instruction 00000 00002 LD NOT 00000 00003 Instruction A LOAD NOT instruction.
Page 54 Basic Ladder Diagrams Section 4-3 spond in order from the top to a LOAD NOT, an OR NOT, and an OR instruc- tion. Again, each of these instructions requires one line of mnemonic code. 00000 Instruction 00100 LR 0000 Address Instruction Operands 00000 00000...
Page 55: Output And Output Not
Basic Ladder Diagrams Section 4-3 4-3-4 OUTPUT and OUTPUT NOT The simplest way to output the results of combining execution conditions is to output it directly with the OUTPUT and OUTPUT NOT. These instructions are used to control the status of the designated operand bit according to the ex- ecution condition.
Page 56: Logic Block Instructions
Basic Ladder Diagrams Section 4-3 Now you have all of the instructions required to write simple input-output pro- grams. Before we finish with ladder diagram basic and go onto inputting the program into the PC, let’s look at logic block instruction (AND LOAD and OR LOAD), which are sometimes necessary even with simple diagrams.
Page 57 Basic Ladder Diagrams Section 4-3 instruction at the right, the logical AND of the execution conditions resulting from these two blocks would have to be taken. AND LOAD does this. The mnemonic code for the ladder diagram is shown below. The AND LOAD in- struction requires no operands of its own, because it operates on previously determined execution conditions.
Page 58 Basic Ladder Diagrams Section 4-3 The following diagram requires AND LOAD to be converted to mnemonic code because three pairs of parallel conditions lie in series. The two means of coding the programs are also shown. 00000 00002 00004 00500 00001 00003 00005...
Page 59 Basic Ladder Diagrams Section 4-3 The following diagram contains only two logic blocks as shown. It is not nec- essary to further separate block b components, because it can coded directly using only AND and OR. 00000 00001 00002 00003 00501 00201 00004...
Page 60 Basic Ladder Diagrams Section 4-3 logic block instruction and the execution condition of the logic block third from the end, and on back to the first logic block that is being combined. Block 00000 00001 00002 00003 00502 00004 00202 Block Block Block...
Page 61 Basic Ladder Diagrams Section 4-3 ever, OR LOAD must be used to combine the top and bottom blocks on both sides, i.e., to combine a1 and a2; b1 and b2. Block Block 00000 00001 00004 00005 00503 00002 00003 00006 00007 Block Block Block...
Page 62 Basic Ladder Diagrams Section 4-3 The following diagram requires an OR LOAD followed by an AND LOAD to code the top of the three blocks, and then two more OR LOADs to complete the mnemonic code. 00000 00001 Address Instruction Operands LR 0000 00000...
Page 63 Basic Ladder Diagrams Section 4-3 00008 combines blocks blocks d and e, the following AND LOAD combines the resulting execution condition with that of block c, etc. Address Instruction Operands 00000 00001 00002 LR 0000 00000 00000 00001 00001 Block b 00002 00002 Block a...
Page 64: Coding Multiple Right-Hand Instructions
Basic Ladder Diagrams Section 4-3 tion condition of block c with the execution condition resulting from the nor- mally closed condition assigned IR 00003. The rest of the diagram can be coded with OR, AND, and AND NOT instructions. The logical flow for this and the resulting code are shown below.
Page 65: The Programming Console
The Programming Console Section 4-4 the instruction line. In the following example, the last instruction line contains one more condition that corresponds to an AND with IR 00004. 00000 00003 Address Instruction Operands HR 0001 00000 00000 00001 00001 00001 00500 00002 00002...
Page 66: Pc Modes
The Programming Console Section 4-4 The gray keys other than the SHIFT key have either the mnemonic name of the instruction or the abbreviation of the data area written on them. The func- tions of these keys are described below. Pressed before the function code when inputting an instruction via its function code.
Page 67 The Programming Console Section 4-4 operation as well as the procedures that are possible from the Programming Console. RUN mode is the mode used for normal program execution. When the switch is set to RUN and the START input on the CPU Power Supply Unit is ON, the CPU will begin executing the program according to the program written in its Program Memory.
Page 68: Preparation For Operation
Preparation for Operation Section 4-5 Caution Always confirm that the Programming Console is in PROGRAM mode when turning on the PC with a Programming Console connected unless another mode is desired for a specific purpose. If the Programming Console is in RUN mode when PC power is turned on, any program in Program Memory will be executed, possibly causing a PC-controlled system to begin operation.
Page 69: Clearing Memory
Preparation for Operation Section 4-5 tered, the PC will shift to the mode set on the mode switch, causing PC op- eration to begin if the mode is set to RUN or MONITOR. The mode can be changed to RUN or MONITOR with the mode switch after entering the pass- word.
Page 70 Preparation for Operation Section 4-5 Key Sequence Program Memory cleared from designated address. Both AR and HR areas TC area Retained if pressed DM area All Clear The following procedure is used to clear memory completely. Continue pressing the CLR key once for each error message until ”00000”...
Page 71: Registering The I/O Table
Preparation for Operation Section 4-5 To leave the TC area uncleared and retaining Program Memory addresses 00000 through 00122, input as follows: 4-5-3 Registering the I/O Table The I/O Table Registration operation writes the types of I/O Units controlled by the PC and the Rack locations of the I/O Units into the I/O table memory area of the CPU (see Section 3-2 I/R Area).
Page 72 Preparation for Operation Section 4-5 Initial I/O Table Registration Memory cleared completely Register I/O table Registering Word When Remote I/O Master Units in the system are connected to I/O Link Multipliers for Masters Units, Optical I/O Units, Remote Terminals, or I/O Terminals a word multiplier between 0 and 3 must be assigned to each one of the Masters after register- ing the I/O table.
Page 73: Clearing Error Messages
Preparation for Operation Section 4-5 word multiplier, do not overlap with the highest I/O words on the last Expan- sion I/O Rack. Automatically checks I/O table. This operation takes about 2 s. Indicates word multiplier not yet specified. Once the word has been specified and entered with the WRITE key, proceed to the next master.
Page 74: Transferring The I/O Table
Preparation for Operation Section 4-5 Key Sequence 4-5-5 Transferring the I/O Table The I/O Table Transfer operation transfers a copy of the I/O table to RAM program memory.This allows the user program and I/O table to be written into EPROM together. Note When power is applied to a PC which has a copy of an I/O table stored in its program memory, the I/O table of the CPU will be overwritten.
Page 75 Preparation for Operation Section 4-5 Change operation allows you to register dummy I/O Units in the I/O table. By reserving an entry in the I/O table with this operation, you can prevent word number discrepancies when an I/O Unit is to be added to the System in the future.
Page 76: Changing I/O Units On-Line (C2000H Only)
Preparation for Operation Section 4-5 Example Reserves space for a 32-point Output Unit. First registration generates this error. Displayed when an I/O verification error has already occurred. Reading a slot with- out a Unit mounted. Reserves space for a 16-point Input Unit. Reserves 2 words.
Page 77: Verifying The I/O Table
Preparation for Operation Section 4-5 Monitoring via AR Bits Function AR 2200 to AR 2211 A 3-digit BCD number indicating the first word of an I/O Unit that is being changed on-line. AR 2212 to AR 2214 A 3-bit number indicating the number of words occupied by the I/O Unit that is being changed on-line.
Page 78: Reading The I/O Table
Preparation for Operation Section 4-5 Key Sequence Example (No errors) (An error occurred) Actual I/O words Registered I/O table words I/O slot number Rack number Meaning of Displays Duplication Indicates a Remote I/O Unit that has not been registered 4-5-9 Reading the I/O Table The I/O Table Read operation is used to access the I/O table that is currently registered in the CPU memory.
Page 79 Preparation for Operation Section 4-5 Example of I/O Unit Mounting Slot number 1 2 3 4 5 6 7 CPU Rack Rack 4 or CPU I/O Rack 0 Rack* 1 2 3 4 5 6 7 Rack 5 Rack 1 Expansion Expansion I/O Racks...
Page 80 Preparation for Operation Section 4-5 Example (When there is no I/O Unit with the specified unit number) Meaning of Displays I/O Unit Designations for Displays No. of points Input Unit Output Unit I/O Units, Special I/O Units, I/O Link Units I/O word number I/O type: I (input), O (output), or N (reserved)
Page 81 Preparation for Operation Section 4-5 Remote I/O Master Unit Word Multiplier (0 to 3) Master number (0 to 7) Remote I/O Slave Racks I/O word number I/O type: I (input), O (output), or N (reserved) I/O slot number Remote I/O Slave Unit number (0 to 7) Remote I/O Master Unit number (0 to 7) Indicates a Remote I/O Rack Interrupt Units...
Page 82: Inputting, Modifying, And Checking The Program
Inputting, Modifying, and Checking the Program Section 4-6 Inputting, Modifying, and Checking the Program Once a program is written in mnemonic code, it can be input directly into the PC from a Programming Console. Mnemonic code is keyed into Program Memory addresses from the Programming Console.
Page 83: Entering Or Editing Programs
Inputting, Modifying, and Checking the Program Section 4-6 Example If the following mnemonic code has already been input into Program Memory, the key inputs below would produce the displays shown. Address Instruction Operands 00200 00000 00201 00001 00202 #0123 00203 00100 4-6-2 Entering or Editing Programs...
Page 84 Inputting, Modifying, and Checking the Program Section 4-6 When inputting an SV as a constant, CONT/# is not required; just input the numeric value and press WRITE. To designate a word, press CLR and then input the word address as described above. Designating Instructions The most basic instructions are input using the Programming Console keys provided for them.
Page 85 Inputting, Modifying, and Checking the Program Section 4-6 Example The following program can be entered using the key inputs shown below. Displays will appear as indicated. Address Instruction Operands 00200 00002 00201 #0123 00202 TIMH(15) #0500 Error Messages The following error messages may appear when inputting a program. Correct the error as indicated and continue with the input operation.
Page 86: Checking The Program
Inputting, Modifying, and Checking the Program Section 4-6 the displays shown below will be replaced with numeric data, normally an address, in the actual display. Message Cause and correction An attempt was made to write to ROM or to write-protected RAM. Be sure a RAM Unit is mounted and that its write-protect switch is set to OFF.
Page 87 Inputting, Modifying, and Checking the Program Section 4-6 Type Message Meaning and appropriate response Type A The program has been lost. Re-enter the program. There is no END(01) in the program. Write END(01) at the final address in the program. The number of logic blocks and logic block instructions does not agree, i.e., either LD or LD NOT has been used to start a logic block whose execution condition has not been used by another instruction, or a logic block instruction has been used that does not have the...
Page 88: Displaying The Cycle Time
Inputting, Modifying, and Checking the Program Section 4-6 Example The following example shows some of the displays that can appear as a re- sult of a program check. Display #1 Halts program check Display #2 Check continues until END(01) Display #3 When errors are found 4-6-4 Displaying the Cycle Time...
Page 89: Program Searches
Inputting, Modifying, and Checking the Program Section 4-6 4-6-5 Program Searches The program can be searched for occurrences of any designated instruction or data area address used in an instruction. Searches can be performed from any currently displayed address or from a cleared display. To designate a bit address, press SHIFT, press CONT/#, then input the ad- dress, including any data area designation required, and press SRCH.
Page 90: Inserting And Deleting Instructions
Inputting, Modifying, and Checking the Program Section 4-6 Example: Instruction Search Example: Bit Search 4-6-6 Inserting and Deleting Instructions In PROGRAM mode, any instruction that is currently displayed can be de- leted or another instruction can be inserted before it. These are not possible in RUN or MONITOR modes.
Page 91 Inputting, Modifying, and Checking the Program Section 4-6 To delete an instruction, display the instruction word of the instruction to be deleted and then press DEL and the up key. All the words for the designated instruction will be deleted. Caution Be careful not to inadvertently delete instructions;...
Page 92 Inputting, Modifying, and Checking the Program Section 4-6 Inserting an Instruction Find the address prior to the insertion point Program After Insertion Address Instruction Operands 00000 00100 00001 00101 00002 00201 00003 AND NOT 00102 00004 OR LD 00005 00103 00006 00105 00007...
Page 93: Branching Instruction Lines
Inputting, Modifying, and Checking the Program Section 4-6 4-6-7 Branching Instruction Lines When an instruction line branches into two or more lines, it is sometimes necessary to use either interlocks or TR bits to maintain the execution condi- tion that existed at a branching point. This is because instruction lines are executed across to a right-hand instruction before returning to the branching point to execute instructions one a branch line.
Page 94 Inputting, Modifying, and Checking the Program Section 4-6 This execution condition is then restored after executing the right-hand in- struction by using the same TR bit as the operand of a LOAD instruction TR 0 Address Instruction Operands 00000 00001 00000 00000 Instruction 1...
Page 95 Inputting, Modifying, and Checking the Program Section 4-6 the bottom versions require fewer instructions and do not require TR bits. In the first example, this is achieved by reorganizing the parts of the instruction block: the bottom one, by separating the second OUTPUT instruction and using another LOAD instruction to create the proper execution condition for Note Although simplifying programs is always a concern, the order of execution of instructions is sometimes important.
Page 96 Inputting, Modifying, and Checking the Program Section 4-6 execution of all instruction up to the next INTERLOCK CLEAR instruction. If the execution condition for the INTERLOCK instruction is OFF, all right-hand instructions through the next INTERLOCK CLEAR instruction will be ex- ecuted with OFF execution conditions to reset the entire section of the ladder diagram.
Page 97: Jumps
Inputting, Modifying, and Checking the Program Section 4-6 tion 1 and then the status of IR 00002 would be loaded to form the execution condition for the second INTERLOCK instruction. If IR 00002 is OFF, instruc- tions 2 through 4 will be executed with OFF execution conditions. If IR 00002 is ON, IR 00003, IR 00005, and IR 00006 will determine the first execution condition in new instruction lines.
Page 98 Inputting, Modifying, and Checking the Program Section 4-6 ber of 00. Although, as in all jumps, no status is changed and no instructions are executed between the JUMP 00 and JUMP END 00 instructions, the pro- gram must search for the next JUMP END 00 instruction, producing a slightly longer execution time.
Page 99: Controlling Bit Status
Controlling Bit Status Section 4-7 Controlling Bit Status There are five instructions that can be used generally to control individual bit status. These are the OUTPUT, OUTPUT NOT, DIFFERENTIATE UP, DIF- FERENTIATE DOWN, and KEEP instructions. All of these instructions ap- pear as the last instruction in an instruction line and take a bit address for an operand.
Page 100: Work Bits (Internal Relays)
Work Bits Section 4-8 one instruction line, the instruction lines are coded first before the instruction that they control. Address Instruction Operands 00002 00003 00000 00002 S: set input KEEP(11) 00001 AND NOT 00003 HR 0000 00002 00004 00004 00003 00005 R: reset input 00004...
Page 101 Work Bits Section 4-8 Work Bit Applications Examples given later in this subsection show two of the most common ways to employ work bits. These should act as a guide to the almost limitless num- ber of ways in which the work bits can be used. Whenever difficulties arise in programming a control action, consideration should be given to work bits and how they might be used to simplify programming.
Page 102: Programming Precautions
Programming Precautions Section 4-9 ple, IR 00100 must be left ON continuously as long as IR 00001 is ON and both IR 00002 and IR 00003 are OFF, or as long as IR 00004 is ON and IR 00005 is OFF. It must be turned ON for only one cycle each time IR 00000 turns ON (unless one of the preceding conditions is keeping it ON continu- ously).
Page 103 Programming Precautions Section 4-9 The number of times any particular bit can be assigned to conditions is not limited, so use them as many times as required to simplify your program. Often, complicated programs are the result of attempts to reduce the number of times a bit is used.
Page 104: Program Execution
Program Execution Section 4-10 4-10 Program Execution When program execution is started, the CPU scans the program from top to bottom, checking all conditions and executing all instructions accordingly as it moves down the bus bar. It is important that instructions be placed in the proper order so that, for example, the desired data is moved to a word before that word is used as the operand for an instruction.
Page 105 SECTION 5 Instruction Set The C1000H and C2000H PC have large programming instruction sets that allow for easy programming of complicated control processes. This section explains each instruction individually and provides the ladder diagram symbol, data areas, and flags used with each. The many instructions provided by the C1000H and C2000H are described in following subsections by instruction group.
Page 106 5-14-3 BLOCK SET – BSET(71) ......... . . 5-14-4 BLOCK TRANSFER –...
Page 107 5-21-3 SET – SET<07> and RESET – RSET<08> ......5-21-4 Block Branching–IF<02>, IF<02>NOT, ELSE<03>, and IEND<04> .
Page 108: Notation
Data Areas, Definer Values, and Flags Section 5-3 Notation In the remainder of this manual, all instructions will be referred to by their mnemonics. For example, the OUTPUT instruction will be called OUT; the AND LOAD instruction, AND LD. If you’re not sure of the instruction a mne- monic is used for, refer to Appendix B Programming Instructions.
Page 109 Data Areas, Definer Values, and Flags Section 5-3 Caution The IR and SR areas are considered as separate data areas. If an operand has access to one area, it doesn’t necessarily mean that the same operand will have access to the other area. The border between the IR and SR areas can, howev- er, be crossed for a single operand, i.e., the last bit in the IR area may be speci- fied for an operand that requires more than one word as long as the SR area is also allowed for that operand.
Page 110: Differentiated Instructions
Coding Right-hand Instructions Section 5-5 Differentiated Instructions Most instructions are provided in both differentiated and non-differentiated forms. Differentiated instructions are distinguished by an @ in front of the instruction mnemonic. A non-differentiated instruction is executed each time it is scanned as long as its execution condition is ON.
Page 111 Coding Right-hand Instructions Section 5-5 gram symbol for all other instructions follows the same pattern, as described below, and is not specified for each instruction individually. The first word of any instruction defines the instruction and provides any de- finers. If the instruction requires only a signal bit operand with no definer, the bit operand is also placed on the same line as the mnemonic.
Page 112 Coding Right-hand Instructions Section 5-5 The following diagram and corresponding mnemonic code illustrates the points described above. Address Instruction Data 00000 00001 DIFU(13) 22500 00000 00000 00002 00001 00001 00002 00002 00003 DIFU(13) 22500 00100 00200 22500 BCNT(67) 00004 00100 01001 01002 LR 6300 #0001...
Page 113: Ladder Diagram Instructions
Ladder Diagram Instructions Section 5-6 LD or LD NOT, to form ‘logic blocks’ that are combined by the right-hand in- struction. An example of this for SFT(10) is shown below. Address Instruction Data 00000 00001 00000 00000 SFT(10) 00002 00001 00001 HR 00 00002...
Page 114: Load, Load Not, And, And Not, Or, And Or Not
Ladder Diagram Instructions Section 5-6 5-6-1 LOAD, LOAD NOT, AND, AND NOT, OR, and OR NOT Ladder Symbols Operand Data Areas B: Bit LOAD - LD IR, SR, AR, HR, TC, LR, TR B: Bit LOAD NOT - LD NOT IR, SR, AR, HR, TC, LR B: Bit AND - AND...
Page 115: Bit Control Instructions
Bit Control Instructions Section 5-7 5-6-2 AND LOAD and OR LOAD AND LOAD - AND LD 00000 00002 Ladder Symbol 00001 00003 OR LOAD - OR LD 00000 00001 Ladder Symbol 00002 00003 Description When instructions are combined into blocks that cannot be logically com- bined using only OR and AND operations, AND LD and OR LD are used.
Page 116: Differentiate Up And Differentiate Down - Difu(13) And Difd(14)
Bit Control Instructions Section 5-7 Description OUT and OUT NOT are used to control the status of the designated bit ac- cording to the execution condition. OUT turns ON the designated bit for an ON execution condition, and turns OFF the designated bit for an OFF execution condition. With a TR bit, OUT appears at a branching point rather than at the end of an instruction line.
Page 117 Bit Control Instructions Section 5-7 These instructions are used when differentiated instructions (i.e., those pre- fixed with an @) are not available and single-cycle execution of a particular instruction is desired. They can also be used with non-differentiated forms of instructions that have differentiated forms when their use will simplify pro- gramming.
Page 118: Keep - Keep(11)
Bit Control Instructions Section 5-7 5-7-3 KEEP – KEEP(11) Ladder Symbol Operand Data Areas B: Bit KEEP(11) IR, AR, HR, LR Limitations Any output bit can generally be used in only one instruction that controls its status. Refer to 3-2 IR Area for details and to 5-20 Block Instructions for in- formation on using output bits in SET<07>...
Page 119: Interlock And Interlock Clear - Il(02) And Ilc(03)
INTERLOCK and INTERLOCK CLEAR – IL(02) and ILC(03) Section 5-8 Input Unit KEEP(11) NEVER HR 0003 Bits used in KEEP are not reset in interlocks. Refer to the 5-7 INTERLOCK and INTERLOCK CLEAR – IL(02) and ILC(03) for details. Example If a HR bit or an AR bit is used, bit status will be retained even during a power interruption.
Page 120 INTERLOCK and INTERLOCK CLEAR – IL(02) and ILC(03) Section 5-8 Instruction Treatment OUT and OUT NOT Designated bit turned OFF. TIM and TIMH(15) Reset. CNT, CNTR(12) PV maintained. KEEP(11) Bit status maintained. DIFU(13) and DIFD(14) Not executed (see below). All others Not executed.
Page 121: Jump And Jump End - Jmp(04) And Jme(05)
JUMP and JUMP END – JMP(04) and JME(05) Section 5-9 Example The following diagram shows IL(02) being used twice with one ILC(03). Address Instruction Operands 00000 IL(02) 00000 00000 00001 IL(02) 00001 TIM 511 00002 00001 #0015 1.5 s 00003 00002 0015 IL(02)
Page 122: End - End(01)
NO OPERATION – NOP(00) Section NO TAG tween JMP(04) and JME(05) are skipped, jump numbers 01 through 99 can be used to reduce cycle time. If the jump number for JMP(04) is 00, the CPU will look for the next JME(05) with a jump number of 00.
Page 123: Timer And Counter Instructions
Timer and Counter Instructions Section 5-12 the program execution moves to the next instruction. When memory is cleared prior to programming, NOP(00) is written at all addresses. NOP(00) can be input through the 00 function code. Flags There are no flags affected by NOP(00). 5-12 Timer and Counter Instructions TIM and TIMH are decrementing ON-delay timer instructions which require a...
Page 124: Timer - Tim
Timer and Counter Instructions Section 5-12 5-12-1 TIMER – TIM Definer Values N: TC number Ladder Symbol # (000 through 511) TIM N Operand Data Areas SV: Set value (word, BCD) IR, AR, DM, HR, LR, # Limitations SV is between 000.0 and 999.9. The decimal point is not entered. Each TC number can be used as the definer in only one timer or counter in- struction.
Page 125 Timer and Counter Instructions Section 5-12 stays ON for at least 15 seconds. When 00000 goes OFF, the timer will be reset and 00200 will be turned OFF. When 00001 goes ON, TIM 001 is started from the SV provided through IR word 005. Bit 00201 is also turned ON when 00001 goes ON.
Page 126 Timer and Counter Instructions Section 5-12 TIM 002 when 00000 goes ON and 00500 is necessary to activate TIM 002 (when 00000 is OFF). 00000 Address Instruction Operands TIM 001 00000 00000 #0050 5.0 s 00001 00500 00000 0050 TIM 002 00002 00500 #0030...
Page 127: High-Speed Timer - Timh(15)
Timer and Counter Instructions Section 5-12 second TIM is started and when the second TIM’s Completion Flag goes ON, the first TIM is started. 00000 TIM 002 Address Instruction Operands TIM 001 00000 00000 #0010 1.0 s 00001 TIM 001 00002 TIM 002 0010...
Page 128: Counter - Cnt
Timer and Counter Instructions Section 5-12 With a C2000H Duplex System, TC 048 through TC 511 cannot be used for TIMH(15). Description TIMH(15) operates in the same way as TIM except that TIMH measures in units of 0.01 second. The cycle time affects TIMH(15) accuracy if TC 048 through TC 511 are used.
Page 129 Timer and Counter Instructions Section 5-12 Changes in execution conditions, the Completion Flag, and the PV are illus- trated below. PV line height is meant only to indicate changes in the PV. Execution condition on count pulse (CP) Execution condition on reset (R) Completion Flag 0002...
Page 130 Timer and Counter Instructions Section 5-12 In the following example, 00000 is used to control when CNT 001 operates. CNT 001, when 00000 is ON, counts down the number of OFF to ON changes in 00001. CNT 001 is reset by its Completion Flag, i.e., it starts counting again as soon as its PV reaches zero.
Page 131: Reversible Counter - Cntr(12)
Timer and Counter Instructions Section 5-12 x 100 times, i.e., 500 seconds (or 8 minutes and 20 seconds) have expired. This would result in 00201 being turned ON. 00000 TIM 001 CNT 002 Address Instruction Operands TIM 001 00000 00000 #0050 00001 AND NOT...
Page 132 Timer and Counter Instructions Section 5-12 The present value (PV) will be incremented by one whenever CNTR(12) is executed with an ON execution condition for II and the last execution condi- tion for II was OFF. The present value (PV) will be decremented by one whenever CNTR(12) is executed with an ON execution condition for DI and the last execution condition for DI was OFF.
Page 133: Data Shifting
Data Shifting Section 5-13 5-13 Data Shifting All of the instructions described in this section are used to shift data, but in differing amounts and directions. The first shift instruction, SFT(10), shifts an execution condition into a shift register; the rest of the instructions shift data that is already in memory.
Page 134 Data Shifting Section 5-13 Example 1: The following example uses the 1-second clock pulse bit (25502) so that the Basic Application execution condition produced by 00005 is shifted into a 3-word register be- tween IR 010 and IR 012 every second. 00005 Address Instruction...
Page 135: Reversible Shift Register - Sftr(84)
Data Shifting Section 5-13 used to detect faulty products in the chute so that the pusher output and HR 0003 of the shift register can be reset as required. Sensor (00001) Pusher (00500) Sensor (00002) Rotary Encoder (00000) Chute 00001 Address Instruction Operands SFT(10)
Page 136 Data Shifting Section 5-13 tion, the status to be put into the register, the shift pulse, and the reset input. The control word is allocated as follows: 15 14 13 12 Not used. Shift direction 1 (ON): Left 0 (OFF): Right Status to input into register Shift pulse bit Reset...
Page 137: Arithmetic Shift Left - Asl(25)
Data Shifting Section 5-13 Example In the following example, IR 00005, IR 00006, IR 00007, and IR 00008 are used to control the bits of C used in @SFTR(84). The shift register is be- tween LR 20 and LR 21, and it is controlled through IR 00009. 00005 05012 Direction...
Page 138: Arithmetic Shift Right - Asr(26)
Data Shifting Section 5-13 5-13-4 ARITHMETIC SHIFT RIGHT – ASR(26) Ladder Symbols Operand Data Areas Wd: Shift word ASR(26) @ASR(26) IR, AR, DM, HR, LR Description When the execution condition is OFF, ASR(25) is not executed. When the execution condition is ON, ASR(25) shifts a 0 into bit 15 of Wd, shifts the bits of Wd one bit to the right, and shifts the status of bit 00 into CY.
Page 139: Rotate Right - Ror(28)
Data Shifting Section 5-13 5-13-6 ROTATE RIGHT – ROR(28) Ladder Symbols Operand Data Areas Wd: Rotate word ROR(28) @ROR(28) IR, AR, DM, HR, LR Description When the execution condition is OFF, ROR(28) is not executed. When the execution condition is ON, ROR(28) shifts all Wd bits one bit to the right, shifting CY into bit 15 of Wd and shifting bit 00 of Wd into CY.
Page 140: One Digit Shift Right - Srd(75)
Data Shifting Section 5-13 Precautions If a power failure occurs during a shift operation across more than 50 words, the shift operation might not be completed. Flags The St and E words are in different areas, or St is greater than E. Indirectly addressed DM word is non-existent.
Page 141: Data Movement
Data Movement Section 5-14 Limitations St and E must be in the same data area, and E must be greater than or equal to St. Description When the execution condition is OFF, WSFT(16) is not executed. When the execution condition is ON, WSFT(16) shifts data between St and E in word units.
Page 142: Move Not - Mvn(22)
Data Movement Section 5-14 5-14-2 MOVE NOT – MVN(22) Ladder Symbols Operand Data Areas S: Source word MVN(22) @MVN(22) IR, SR, AR, DM, HR, TC, LR, # D: Destination word IR, AR, DM, HR, LR Description When the execution condition is OFF, MVN(22) is not executed. When the execution condition is ON, MVN(22) transfers the complement of the content of S (specified word or four-digit hexadecimal constant) to D, i.e., for each ON bit in S, the corresponding bit in D is turned OFF, and for each OFF bit in...
Page 143 Data Movement Section 5-14 Description When the execution condition is OFF, BSET(71) is not executed. When the execution condition is ON, BSET(71) copies the content of S to all words from St through E. 3 4 5 3 4 5 St+1 3 4 5 St+2...
Page 144: Block Transfer - Xfer(70)
Data Movement Section 5-14 5-14-4 BLOCK TRANSFER – XFER(70) Operand Data Areas N: Number of words (BCD) Ladder Symbols IR, SR, AR, DM, HR, TC, LR, # XFER(70) @XFER(70) S: Starting source word IR, SR, AR, DM, HR, TC, LR D: Starting destination word IR, AR, DM, HR, TC, LR Limitations...
Page 145: Single Word Distribute - Dist(80)
Data Movement Section 5-14 If you want to exchange content of blocks whose size is greater than 1 word, use work words as an intermediate buffer to hold one of the blocks using XFER(70) three times. Indirectly addressed DM word is non-existent. (Content of *DM word Flags is not BCD, or the DM area boundary has been exceeded.) 5-14-6...
Page 146: Move Bit - Movb(82)
Data Movement Section 5-14 Limitations Of must be a BCD. SBs must be in the same data area as SBs+Of. Description When the execution condition is OFF, COLL(81) is not executed. When the execution condition is ON, COLL(81) copies the content of SBs + Of to D, i.e., Of is added to SBs to determine the source word.
Page 147: Move Digit - Movd(83)
Data Movement Section 5-14 5-14-9 MOVE DIGIT – MOVD(83) Operand Data Areas S: Source word Ladder Symbols IR, SR, AR, DM, HR, TC, LR, # MOVD(83) @MOVD(83) Di: Digit designator (BCD) IR, AR, DM, HR, TC, LR, # D: Destination word IR, AR, DM, HR, TC, LR Limitations The rightmost three digits of Di must each be between 0 and 3.
Page 148: Data Comparison
Data Comparison Section 5-15 5-15 Data Comparison This section describes the instructions used for comparing data. CMP(20) is used to compare the contents of two words; BCMP(68) is used to determine within which of several preset ranges the content of one word lies; and TCMP(85) is used to determine which of several preset values the content of one word equals.
Page 149 Data Comparison Section 5-15 this type of programming, 00200, 00201, and 00202 are changed only when CMP(20) is executed. 00000 CMP(20) HR 09 25505 00200 Greater Than 25506 00201 Equal 25507 00202 Less Than Address Instruction Operands Address Instruction Operands 00000 00000 00005...
Page 150 Data Comparison Section 5-15 Because all of the comparisons here use to the timer’s PV as reference, the other operand for each CMP(20) must be in 4-digit BCD. 00000 TIM 010 #5000 CMP(20) TIM 010 #4000 25507 Output at 00200 100 s.
Page 151: Block Compare - Bcmp(68)
Data Comparison Section 5-15 5-15-2 BLOCK COMPARE – BCMP(68) Operand Data Areas CD: Compare data Ladder Symbols IR, SR, DM, HR, TC, LR, # BCMP(68) @BCMP(68) CB: First comparison block word IR, SR, DM, HR, TC, LR R: Result word IR, AR, DM, HR, TC, LR Limitations Each lower limit word in the comparison block must be less than or equal to...
Page 152 Data Comparison Section 5-15 Example The following example shows the comparisons made and the results pro- vided for BCMP(68). Here, the comparison is made during each cycle when 00000 is ON. Address Instruction Operands 00000 BCMP(68) 00000 00000 00001 BCMP(68) HR 10 HR 05 CD: 001...
Page 153 Data Comparison Section 5-15 Example The following example shows the comparisons made and the results pro- vided for TCMP(85). Here, the comparison is made during each cycle when 00000 is ON. Address Instruction Operands 00000 TCMP(85) 00000 00000 00001 TCMP(85) HR 10 HR 05 CD: 001...
Page 154: Data Conversion
Data Conversion Section 5-16 5-16 Data Conversion The conversion instructions convert word data that is in one format into an- other format and output the converted data to specified result word(s). Con- versions are available to convert between binary (hexadecimal) and BCD, to 7-segment display data, to ASCII, and between multiplexed and non-multi- plexed data.
Page 155: Binary-To-Bcd - Bcd(24)
Data Conversion Section 5-16 Description When the execution condition is OFF, BINL(58) is not executed. When the execution condition is ON, BINL(58) converts an eight-digit number in S and S+1 into 32-bit binary data, and outputs the converted data to R and R+1. S + 1 R + 1 Binary...
Page 156: Double Binary-To-Double Bcd - Bcdl(59)
Data Conversion Section 5-16 5-16-4 DOUBLE BINARY-TO-DOUBLE BCD – BCDL(59) Ladder Symbols Operand Data Areas S: First source word (binary) BCDL(59) @BCDL(59) IR, SR, AR, DM, HR, LR R: First result word IR, AR, DM, HR, LR Limitations If the content of S exceeds 05F5E0FF, the converted result would exceed 99999999 and BCDL(59) will not be executed.
Page 157 Data Conversion Section 5-16 value is then turned ON in a result word. If more than one digit is specified, then one bit will be turned ON in each of consecutive words beginning with R. (See examples, below.) The following is an example of a one-digit decode operation from digit num- ber 1 of S, i.e., here Di would be 0001.
Page 158: 16-To-4 Encoder - Dmpx(77)
Data Conversion Section 5-16 Example The following program converts three digits of data from DM 0020 to bit posi- tions and turns ON the corresponding bits in three consecutive words starting with HR 10. 00000 Address Instruction Operands MLPX(76) 00000 00000 DM 0020 00001...
Page 159 Data Conversion Section 5-16 The following is an example of a one-digit encode operation to digit number 1 of R, i.e., here Di would be 0001. First source word C transferred to indicate bit number 12 as the highest ON bit. Result word Up to four digits from four consecutive source words starting with S may be encoded and the digits written to R in order from the designated first digit.
Page 160: 7-Segment Decoder - Sdec(78)
Data Conversion Section 5-16 digits of HR 20. Although the status of each source word bit is not shown, it is assumed that the bit with status 1 (ON) shown is the highest bit that is ON in the word. 00000 Address Instruction Operands...
Page 161 Data Conversion Section 5-16 Any or all of the digits in S may be converted in sequence from the desig- nated first digit. The first digit, the number of digits to be converted, and the half of D to receive the first 7-segment display code (rightmost or leftmost 8 bits) are designated in Di.
Page 162 Data Conversion Section 5-16 The table underneath shows the original data and converted code for all hex- adecimal digits. Bit 00 bit 08 1: Second digit 0: One digit Bit 07 bit 15 0 or 1: bits 00 through 07 or 08 through 15.
Page 163: Ascii Convert - Asc(86)
Data Conversion Section 5-16 5-16-8 ASCII CONVERT – ASC(86) Operand Data Areas S: Source word Ladder Symbols IR, SR, AR, DM, HR, TC, LR ASC(86) @ASC(86) Di: Digit designator IR, AR, DM, HR, TC, LR, # D: First destination word IR, AR, DM, HR, LR Limitations Di must be within the values given below...
Page 164: Bcd Calculations
BCD Calculations Section 5-17 Some examples of Di values and the 4-bit binary to 8-bit ASCII conversions that they produce are shown below. Di: 0011 Di: 0030 1st half 1st half 2nd half 2nd half 1st half 2nd half Di: 0112 Di: 0130 1st half 1st half...
Page 165: Increment - Inc(38)
BCD Calculations Section 5-17 The addition and subtraction instructions include CY in the calculation as well as in the result. Be sure to clear CY if its previous status is not required in the calculation, and to use the result placed in CY, if required, before it is changed by execution of any other instruction.
Page 166: Bcd Add - Add(30)
BCD Calculations Section 5-17 When the execution condition is OFF, CLC(41) is not executed.When the ex- ecution condition is ON, CLC(41) turns OFF CY (SR 25504). 5-17-5 BCD ADD – ADD(30) Operand Data Areas Au: Augend word (BCD) Ladder Symbols IR, SR, AR, DM, HR, TC, LR, # ADD(30) @ADD(30)
Page 167: Double Bcd Add - Addl(54)
BCD Calculations Section 5-17 5-17-6 DOUBLE BCD ADD – ADDL(54) Operand Data Areas Au: First augend word (BCD) Ladder Symbols IR, SR, AR, DM, HR, TC, LR ADDL(54) @ADDL(54) Ad: First addend word (BCD) IR, SR, AR, DM, HR, TC, LR R: First result word IR, AR, DM, HR, LR Description...
Page 168: Bcd Subtract - Sub(31)
BCD Calculations Section 5-17 00000 Address Instruction Operands CLC(41) 00000 00000 @ADDL(54) 00001 CLC(41) LR 20 00002 @ADDL(54) DM 0010 HR 10 0010 @ADD(30) 00003 @ADD(30) LR 22 DM 0012 0012 HR 12 @ADB(50) 00004 @ADB(50) #0000 0000 #0000 0000 HR 13 5-17-7 BCD SUBTRACT –...
Page 169 BCD Calculations Section 5-17 If CY is set by executing SUB(31), the result in HR 20 is subtracted from zero (note that CLC(41) is again required to obtain an accurate result), the result is placed back in HR 20, and HR 2100 is turned ON to indicate a negative result.
Page 170: Double Bcd Subtract - Subl(55)
BCD Calculations Section 5-17 Second Subtraction 0000 HR 20 –7577 –0 HR 20 2423 (0000 + (10000 – 7577)) (negative result) In the above case, the program would turn ON HR 2100 to indicate that the value held in HR 20 is negative. 5-17-8 DOUBLE BCD SUBTRACT –...
Page 171: Bcd Multiply - Mul(32)
BCD Calculations Section 5-17 and DM 0001 so that a negative result can be subtracted from 0 (inputting an 8-digit constant is not possible). TR 0 00003 CLC(41) @SUBL(55) First subtraction HR 20 DM 0100 25504 @BSET(71) #0000 DM 0000 DM 0001 CLC(41) Second...
Page 172: Double Bcd Multiply - Mull(56)
BCD Calculations Section 5-17 Description When the execution condition is OFF, MUL(32) is not executed. When the execution condition is ON, MUL(32) multiplies Md by the content of Mr, and places the result In R and R+1. R +1 Example When IR 00000 is ON with the following program, the contents of IR 013 and DM 0005 are multiplied and the result is placed in HR 07 and HR 08.
Page 173: Bcd Divide - Div(33)
BCD Calculations Section 5-17 Description When the execution condition is OFF, MULL(56) is not executed. When the execution condition is ON, MULL(56) multiplies the eight-digit content of Md and Md+1 by the content of Mr and Mr+1, and places the result in R to R+3. Md + 1 Mr + 1 R + 1...
Page 174: Double Bcd Divide - Divl(57)
BCD Calculations Section 5-17 Example When IR 00000 is ON with the following program, the content of IR 020 is divided by the content of HR 09 and the result is placed in DM 0017 and DM 0018. Example data and calculations are shown below the program. 00000 Address Instruction Operands...
Page 175: Floating Point Divide - Fdiv(79)
BCD Calculations Section 5-17 5-17-13 FLOATING POINT DIVIDE – FDIV(79) Operand Data Areas Dd: First dividend word (BCD) Ladder Symbols IR, SR, AR, DM, HR, TC, LR FDIV(79) @FDIV(79) Dr: First divisor word (BCD) IR, SR, AR, DM, HR, TC, LR R: First result word IR, AR, DM, HR LR Limitations...
Page 176 BCD Calculations Section 5-17 Valid Ranges for Division Data and Quotient Maximum value for division Contents of words data and quotient (same) Dd+1, Dr+1, or R+1 0.9999999×10 Contents of words Dd, Dr, or R Minimum value for Contents of words division data Dd +1 or Dr+1 –7...
Page 177 BCD Calculations Section 5-17 00000 @MOV(21) HR 01 HR 00 #0000 HR 00 @MOV(21) 0000 #0000 HR 02 @MOV(21) HR 01 HR 00 #4000 HR 01 @MOV(21) 4000 #4000 HR 03 DM 0000 @MOVD(83) DM 0000 #0021 HR 01 HR 00 HR 01 @MOVD(83) DM 0000...
Page 178: Square Root - Root(72)
BCD Calculations Section 5-17 5-17-14 SQUARE ROOT – ROOT(72) Ladder Symbols Operand Data Areas Sq: First source word (BCD) ROOT(72) @ROOT(72) IR, SR, AR, DM, HR, TC, LR R: Result word IR, AR, DM, HR, LR, Description When the execution condition is OFF, ROOT(72) is not executed. When the execution condition is ON, ROOT(72) computes the square root of the eight-digit content of Sq and Sq+1 and places the result in R.
Page 179 BCD Calculations Section 5-17 00000 @BSET(71) DM 0101 DM 0100 #0000 DM 0100 DM 0101 0000 0000 @MOV(21) DM 0101 DM 0101 DM 0100 @ROOT(72) DM 0100 60170000= 7756.932 DM 0102 @MOV(21) #0000 DM 0103 IR 011 @MOV(21) 0000 0000 #0000 DM 0103 @MOVD(83)
Page 180: Binary Calculations
Binary Calculations Section 5-18 5-18 Binary Calculations The binary calculation instructions – ADB(50), SBB(51), MLB(52) and DVB(53) – all perform arithmetic operations on hexadecimal data. The addition and subtraction instructions include CY in the calculation as well as in the result. Be sure to clear CY if its previous status is not required in the calculation, and to use the result placed in CY, if required, before it is changed by the execution of any other instruction.
Page 181 Binary Calculations Section 5-18 In the case below, A6E2 + 80C5 = 127A7. The result is a 5-digit number, so CY (SR 25504) = 1, and the content of R + 1 becomes #0001. Au: IR 010 Ad: DM 0100 R+1: HR 11 R: HR 10 The following example performs eight-digit addition by using ADB(50) twice.
Page 182: Binary Subtract - Sbb(51)
Binary Calculations Section 5-18 5-18-2 BINARY SUBTRACT – SBB(51) Operand Data Areas Mi: Minuend word (binary) Ladder Symbols IR, SR, AR, DM, HR, TC, LR, # SBB(51) @SBB(51) Su: Subtrahend word (binary) IR, SR, AR, DM, HR, TC, LR, # R: Result word IR, AR, DM, HR, LR Description...
Page 183 Binary Calculations Section 5-18 HR 11, and either 0000 or 0001 is placed in HR 12 (0001 indicates a nega- tive answer). Address Instruction Operands TR 0 00000 00000 00000 CLC(41) 00001 00002 CLC(41) SBB(51) 00003 SBB(51) DM 0100 0100 HR 10 00004 SBB(51)
Page 184: Binary Multiply - Mlb(52)
Binary Calculations Section 5-18 #0000 – 6851 –1 (from CY = 1) = 0000 + (10000 – 6851 – 1) = 97AE. The content of HR 12, #0001, indicates a negative result. Lower 4 digits. Higher 4 digits. Mi: IR 010 Mi: IR 011 Su: DM 0100 Su: DM 0101...
Page 185: Logic Instructions
Logic Instructions Section 5-19 5-18-4 BINARY DIVIDE – DVB(53) Operand Data Areas Dd: Dividend word (binary) Ladder Symbols IR, SR, AR, DM, HR, TC, LR, # DVB(53) @DVB(53) Dr: Divisor word (binary) IR, SR, AR, DM, HR, TC, LR, # R: First result word IR, AR, DM, HR LR Description...
Page 186: And Word - Andw(34)
Logic Instructions Section 5-19 Indirectly addressed DM word is non-existent. (Content of *DM word Flags is not BCD, or the DM area boundary has been exceeded.) ON when the result is 0. 5-19-2 AND WORD – ANDW(34) Operand Data Areas Ladder Symbols I1: Input 1 IR, SR, AR, DM, HR, TC, LR, #...
Page 187: Exclusive Or - Xorw(36)
Logic Instructions Section 5-19 Description When the execution condition is OFF, ORW(35) is not executed. When the execution condition is ON, ORW(35) logically OR’s the contents of I1 and I2 bit-by-bit and places the result in R. Example Indirectly addressed DM word is non-existent. (Content of *DM word Flags is not BCD, or the DM area boundary has been exceeded.) ON when the result is 0.
Page 188: Subroutines And Interrupt Control
Subroutines and Interrupt Control Section 5-20 5-19-5 EXCLUSIVE NOR – XNRW(37) Operand Data Areas I1: Input 1 Ladder Symbols IR, SR, AR, DM, HR, TC, LR, # XNRW(37) @XNRW(37) I2: Input 2 IR, SR, AR, DM, HR, TC, LR, # R: Result word IR, AR, DM, HR, LR Description...
Page 189: Subroutine Start And Return - Sbn(92)/Ret(93)
Subroutines and Interrupt Control Section 5-20 at the same time. To effectively deal with this, the PC employs a priority sys- tem for handling interrupts. In the case of the scheduled interrupt, the time interval between interrupts is set by the user and is unrelated to the cycle timing of the PC. This capability is useful for periodic supervisory or executive program execution.
Page 190 Subroutines and Interrupt Control Section 5-20 Description A subroutine can be executed by placing SBS(91) in the main program at the point where the subroutine is desired. The subroutine number used in SBS(91) indicates the desired subroutine. When SBS(91) is executed (i.e., when the execution condition for it is ON), the instructions between the SBN(92) with the same subroutine number and the first RET(93) after it are executed before execution returns to the instruction following the SBS(91)
Page 191: Interrupt Control - Int(89)
Subroutines and Interrupt Control Section 5-20 The following diagram illustrates program execution flow for various execu- tion conditions for two SBS(91). SBS(91) OFF execution conditions for subroutines 00 and 01 Main program SBS(91) ON execution condition for subroutine 00 only ON execution condition for SBN(92) subroutine 01 only...
Page 192 Subroutines and Interrupt Control Section 5-20 Description INT(89) is used both to control interrupts from Interrupt Input Units and to control the scheduled interrupt. If N is 000, 001, 002, or 003, it indicates an Interrupt Input Unit number and INT(89) is used to control interrupts from the designated Unit.
Page 193 Subroutines and Interrupt Control Section 5-20 for it will be run as soon as the bit is unmasked (unless it is cleared first – see below). All interrupts are initially masked. CC = 001 A control code of CC = 001 causes the masks on those bits of the designated (Clear) Interrupt Input Unit, corresponding to ON bits in D to be cleared so that the subroutine will not be executed even if the interrupt is unmasked.
Page 194 Subroutines and Interrupt Control Section 5-20 Indirectly addressed DM word is non-existent. (Content of *DM word is not BCD, or the DM area boundary has been exceeded.) Examples The following program shows the overall structure and operation of the scheduled interrupt. Here, the scheduled subroutine is started and will be repeated every 20 ms.
Page 195 Subroutines and Interrupt Control Section 5-20 Interrupt Priority Levels When an interrupt is being serviced (i.e. the subroutine is executing), another incoming interrupt must wait until the first is finished before it will be serviced. Interrupt input #1 Interrupt #1 servicing Interrupt input #2 Interrupt #2 servicing If two or more interrupt inputs are turned ON simultaneously, the subroutine...
Page 196: Block Programming Instructions
Block Programming Instructions Section 5-21 5-21 Block Programming Instructions Block programming facilitates coding operations which are difficult to write with normal ladder diagrams, i.e. ladder diagrams which include sequential arithmetic operations or conditional branching. It also reduces the overall cycle time. Up to 100 block programs may be defined in a given main pro- gram.
Page 197: Set - Set<07> And Reset - Rset<08
Block Programming Instructions Section 5-21 5-21-3 SET – SET<07> and RESET – RSET<08> Operand Data Areas Instruction Formats B: Bit SET<07> IR, AR, HR, LR RSET<08> Description SET<07> turns B ON, and RSET<08> turns B OFF. Flags No flags are affected by this instruction. 5-21-4 Block Branching–IF<02>, IF<02>NOT, ELSE<03>, and IEND<04>...
Page 198 Block Programming Instructions Section 5-21 IF<02> NOT with an IF<02> NOT to ELSE to IEND Operand IF<02> NOT B When B is OFF, C is executed. ELSE<03> When B is ON, D is executed. IEND<04> IF<02> without an Operand IF<02> to ELSE to IEND LD 00000 AND 00001 IF<02>...
Page 199: One Cycle And Wait - Wait<05
Block Programming Instructions Section 5-21 00000 Address Instruction Operands BPRG(96) 00 00000 00000 00001 BPRG(96) IF<02> 00001 00002 IF<02> 00001 CLC(41) ADD(30) 00003 CLC(41) 00004 ADD(30) #0001 DM 0000 ELSE<03> 0001 CLC(41) 0000 ADD(30) 00005 ELSE<03> #0002 00006 CLC(41) DM 0000 00007 ADD(30) IEND<04>...
Page 200 Block Programming Instructions Section 5-21 first cycle. During following cycles, none of the block program will be ex- ecuted until the operand bit or execution condition changes, at which point the remainder of the block program will be executed. Once the entire block program has been executed, the process is repeated.
Page 201: Timer Wait - Timw<13> And High-Speed Timer Wait - Tmhw<15
Block Programming Instructions Section 5-21 5-21-6 TIMER WAIT – TIMW<13> and HIGH-SPEED TIMER WAIT – TMHW<15> Definer Data Areas Instruction Formats N: Timer number TIMW<13> TMHW<15> Operand Data Areas SV: Set value (BCD) IR, AR, DM, HR, LR, # Limitations SV is between 000.0 and 999.9 for TIMW<13>, and between 00.00 and 99.99 for TMHW<15>.
Page 202: Counter Wait - Cntw<14
Block Programming Instructions Section 5-21 5-21-7 COUNTER WAIT – CNTW<14> Definer Data Areas Instruction Format N: Counter number CNTW<14> Operand Data Areas SV: Set value (BCD) IR, AR, DM, HR, LR, # I: Count input IR, SR, AR, HR, TC, LR Limitations Each TC number can be used as the definer in only one timer or counter in- struction, including the normal ladder-diagram timers and counters.
Page 203: Conditional Block Exit - Exit<06> And Exit<06> Not
Block Programming Instructions Section 5-21 5-21-8 CONDITIONAL BLOCK EXIT – EXIT<06> and EXIT<06> NOT Operand Data Areas Instruction Formats B: Bit EXIT<06> IR, SR, AR, HR, TC, LR EXIT<06> EXIT<06> NOT Description EXIT<06> and EXIT<06> NOT conditionally end execution of the block pro- gram in which they occur, based on either the execution condition or the op- erand bit.
Page 204: Block Program Pause - Bpps<11> And Block Program Restart - Bprs<12
Block Programming Instructions Section 5-21 is reached, program execution will loop back to the next previous LOOP<09> an exit condition is attained. A YES LOOP END condition is produced by an ON execution condition for LEND<10> without an operand, by an ON bit for LEND<10> with an operand bit, or by an OFF bit for LEND<10>...
Page 205: Step Instructions
Step Instructions Section 5-22 program that was suspended is then restarted after 10 seconds. Note that the ladder diagram simply has the mnemonic code typed after the BPRG(96) instruction. 00000 BPRG(96) 00 Address Instruction Operands 00000 00000 00001 BPRG(96) IF<02> 00001 00002 IF<02>...
Page 206 Step Instructions Section 5-22 gram so that it is executed before the program reaches the step it starts. It can be used at different locations before the step to control the step accord- ing to two different execution conditions (see example 2, below). Any step in the program that has not been started with SNXT(09) will not be executed.
Page 207 Step Instructions Section 5-22 Precautions Interlocks, jumps, SBN(92), and END(01) cannot be used within step pro- grams. Bits used as control bits must not be used anywhere else in the program un- less they are being used to control the operation of the step (see example 3, below).
Page 208 Step Instructions Section 5-22 Example 1: The following process requires that three processes, loading, part installa- Sequential Execution tion, and inspection/discharge, be executed in sequence with each process being reset before continuing on the the next process. Various sensors (SW1, SW2, SW3, and SW4) are positioned to signal when processes are to start and end.
Page 209 Step Instructions Section 5-22 the next step. Each step starts when the switch that indicates the previous step has been completed turns ON. 00001 (SW1) Process A started. SNXT(09) 12800 STEP(08) 12800 Programming for process A 00002 (SW2) Process A reset. SNXT(09) 12801 Process B started.
Page 210 Step Instructions Section 5-22 Example 2: The following process requires that a product is processed in one of two Branching Execution ways, depending on its weight, before it is printed. The printing process is the same regardless of which of the first processes is used. Various sensors are positioned to signal when processes are to start and end.
Page 211 Step Instructions Section 5-22 start either process A or process B. Both of the steps for these processes end with a SNXT(09) that starts the step for process C. 00001 (SW A1) 00002 (SW B2) SNXT(09) HR 0000 00001 (SW A1) 00002 (SW B2) SNXT(09) HR 0001 Process A started.
Page 212 Step Instructions Section 5-22 Example 3: The following process requires that two parts of a product pass simultane- Parallel Execution ously through two processes each before they are joined together in a fifth process. Various sensors are positioned to signal when processes are to start and end.
Page 213 Step Instructions Section 5-22 Process B is thus reset directly and process D is reset indirectly before exe- cuting the step for process E. 00001 (SW1 and SW2)) Process A started. SNXT(09) LR 0000 Process C started. SNXT(09) LR 0002 STEP(08) LR 0000 Programming for process A 00002 (SW3)
Page 214: Special Instructions
Special Instructions Section 5-23 Address Instruction Operands Address Instruction Operands 00000 00001 00102 STEP(08) 0002 00001 SNXT(09) 0000 00002 SNXT(09) 0002 Process C 00003 STEP(08) 0000 00200 00003 Process A 00201 SNXT(09) 0003 00202 STEP(08) 0003 00100 00002 00101 SNXT(09) 0001 Process D 00102...
Page 215: Display Message - Msg(46)
Special Instructions Section 5-23 When FAL(06) is executed with an ON execution condition, the warning indi- cator on the front of the CPU will light, but PC operation will continue. When FALS(07) is executed with an ON execution condition, the alarm indicator will light and PC operation will stop.
Page 216 Special Instructions Section 5-23 If the message data changes while the message is being displayed, the dis- play will also change. Indirectly addressed DM word is non-existent. (Content of *DM word Flags is not BCD, or the DM area boundary has been exceeded.) Example The following example shows the display that would be produced for the in- struction and data given when 00000 was ON.
Page 217: Data Tracing (Trace Memory Sampling - Trsm(45))
Data Tracing (TRACE MEMORY SAMPLING – TRSM(45)) Section 5-24 5-23-4 WATCHDOG TIMER REFRESH– WDT(94) Ladder Symbols Definer Data Areas T: Watchdog timer value WDT(94) T @WDT(94) T # (00 to 63) Description When the execution condition is OFF, WDT(94) is not executed. When the execution condition is ON, WDT(94) extends the setting of the watchdog tim- er (normally set by the system to 130 ms) by 100 ms times T.
Page 218 Data Tracing (TRACE MEMORY SAMPLING – TRSM(45)) Section 5-24 from a Programming Console. Data tracing is described in detail in the GPC, FIT, and LSS Operation Manuals. This section shows the ladder symbol for TRSM(45) and gives an example program. Address tracing also aids debugging and is possible from the Programming Console.
Page 219 Data Tracing (TRACE MEMORY SAMPLING – TRSM(45)) Section 5-24 00000 Starts data tracing. 1814 Designates point for TRSM(45) tracing. AR 1813 ON when tracing 00200 AR 1812 ON when trace is complete Indicates that tracing has 00201 been completed. Address Instruction Operands Address Instruction Operands...
Page 220: File Memory Instructions
File Memory Instructions Section 5-25 Sampling AR 1815 Start tracing AR 1814 No delay Tracing Flag AR 1813 *Negative Positive delay delay Trace Completed Flag AR 1812 Sampling Trace memory AR 1812 turns ON and the trace is complete when enough data to fill trace memory has been sampled.
Page 221: File Memory Read - Filr(42)
File Memory Instructions Section 5-25 5-25-1 FILE MEMORY READ – FILR(42) Operand Data Areas Ladder Symbols N: Number of transfer blocks (BCD) FILR(42) @FILR(42) IR, AR, DM, HR, TC, LR, # S: Source beginning block (BCD) IR, AR, DM, HR, TC, LR, # D: Destination beginning word IR, AR, DM, HR, TC, LR Limitations...
Page 222: File Memory Write - Filw(43)
File Memory Instructions Section 5-25 5-25-2 FILE MEMORY WRITE – FILW(43) Operand Data Areas Ladder Symbols N: Number of transfer blocks (BCD) FILW(43) @FILW(43) IR, SR, AR, DM, HR, TC, LR, # S: Source beginning word IR, SR, AR, DM, HR, TC, LR D: First destination block (BCD) IR, AR, DM, HR, TC, LR, # Limitations...
Page 223: Intelligent I/O Instructions
Intelligent I/O Instructions Section 5-26 Limitations BB must be less than the largest block number provided by the File Memory Unit (0999 or 1999). The Memory Unit must be RAM, and the blocks being transferred from the File Memory must contain program data. Description When the execution condition is OFF, FILP(44) is not executed.
Page 224: I/O Write - Writ(87)
Intelligent I/O Instructions Section 5-26 5-26-1 I/O WRITE – WRIT(87) Operand Data Areas Ladder Symbols N: Number of transfer words (BCD) WRIT(87) @WRIT(87) IR, AR, DM, HR, TC, LR, # S: Source beginning word IR, SR, AR, DM, HR, TC, LR D: Destination word IR (I/O word only) Limitations...
Page 225: Network Instructions
Network Instructions Section 5-27 Flags S is not allocated to an intelligent I/O Unit. D+(N–1) exceeds a data area boundary. N is not BCD. Indirectly addressed DM word is non-existent. (Content of *DM word is not BCD, or the DM area boundary has been exceeded.) OFF while data is being read;...
Page 226 Network Instructions Section 5-27 *The node number of the PC executing the send may be set. SYSMAC LINK Systems Set the destination node number to 0 to send the data to all nodes. Refer to the SYSMAC LINK System Manual for details. Word Bits 00 to 07 Bits 08 to 15...
Page 227: Network Receive - Recv(98)
Network Instructions Section 5-27 5-27-2 NETWORK RECEIVE – RECV(98) Operand Data Areas Ladder Symbols S: Source beginning word RECV(98) @RECV(98) IR, SR, AR, DM, HR, TC, LR D: Destination beginning word IR, AR, DM, HR, TC, LR C: First control data word IR, AR, DM, HR, TC, LR Limitations C through C+2 must be within the same data area and must be within the...
Page 228: About Sysmac Net Link/Sysmac Link Operations
Network Instructions Section 5-27 Examples This example is for a SYSMAC NET Link System. When 00000 is ON, the following program transfers the content of IR 001 through IR 005 to LR 20 through LR 24 on node 10. 00000 Address Instruction Operands RECV(98)
Page 229 Network Instructions Section 5-27 Timing Successful send/receive execution Send/receive error Instruction Transmission Instruction Transmission Instruction received completes received error received normally Data Processing for Data is transmitted for SEND(90) and RECV(98) for all PCs when SEND(90)/RECV(98) SEND(90)/RECV(98) is executed. Final processing for transmissions/recep- tions is performed when END(01) is executed in C2000H Duplex CPUs, and during servicing of peripheral devices and Link Units for all other CPUs.
Page 230 Network Instructions Section 5-27 SEND(90)/RECV(98) Enable Flag 00000 25204 12802 12800 prevents execution of SEND(90) until KEEP(11) 12800 RECV(98) (below) has completed. IR 00000 is turned ON to start transmission. 12801 12800 @MOV(21) #000A DM 0000 @MOV(21) #0000 DM 0001 Data is placed into control data words to specify the 10 words to be transmitted to @MOV(21)
Page 231 Network Instructions Section 5-27 Address Instruction Operands Address Instruction Operands 00000 00000 00019 AND NOT 12800 00001 25204 00020 12803 00002 AND NOT 12802 00021 KEEP(11) 12802 00003 12801 00022 12802 00004 KEEP(11) 12800 00023 25204 00005 12800 00024 AND NOT 25203 00006 @MOV(21)
Page 232: Program Execution Timing
SECTION 6 Program Execution Timing The timing of various operations must be considered both when writing and debugging a program. The time required to execute the program and perform other CPU operations is important, as is the timing of each signal coming into and leav- ing the PC in order to achieve the desired control action at the right time.
Page 233 Cycle Time Section 6-1 Cycle Time To aid in PC operation, the average, maximum, and minimum cycle times can be displayed on the Programming Console or any other Programming Device and the maximum cycle time and current cycle time values are held in AR 26 and AR 27.
Page 234 Cycle Time Section 6-1 The overall flow of CPU operation is as shown in the following flowchart: Power application Clears IR area and resets all timers Checks I/O Unit connections Resets watchdog timer Checks hardware and Program Memory Check OK? Sets error flags and lights indicator Refresh output signals...
Page 235 Cycle Time Section 6-1 the time that is required for the CPU to complete one of these cycles. This cycle includes basically four types of operation. Overseeing Output refreshing and Unit servicing Input refreshing Program execution The cycle time is the total time required for the PC to perform all of the above operations.
Page 236 Cycle Time Section 6-1 than is required for output refreshing and Unit servicing, Link Units (except for Remote I/O Units) and all peripheral devices will be serviced again, one type at a time, until program execution is completed. From the second cycle on, servicing will be in the following cycle (with servic- ing for the remaining time in any one cycle starting where servicing was left off the previous cycle): PC Link Unit servicing I, PC Link Unit servicing II, pe- ripheral devices, and then Host Link Unit servicing.
Page 237: Calculating Cycle Time
Calculating Cycle Time Section 6-2 Cycle time (ms) Possible adverse affects 10 or greater TIMH(15) inaccurate when TC 048 through TC 511 are used. 20 or greater 0.02-second clock pulse not accurately readable. 100 or greater 0.1-second clock pulse not accurately readable and Cycle Timer Error Flag (25309) turns ON.
Page 238: Pc With Link Units
Calculating Cycle Time Section 6-2 The overseeing time is fixed at 3.0 ms. The input refresh time would be as follows for the five 16-point Input Units and two 32-point Input Units con- trolled by the PC: (16 points x 5) + (32 points x 2) x 25 µs = 0.23 ms 16 points The output refreshing and Unit servicing time equals the I/O bus check time plus the output refresh time plus the peripheral device and Link Unit servicing...
Page 239 Calculating Cycle Time Section 6-2 below. It is assumed that the program contains 20,000 instructions requiring an average of 0.6 µs each to execute. CPU Rack 16-point 16-point Input Output Unit Unit CPU I/O Rack Next PC in Computer PC Link System Host Link Unit PC Link Unit Optical Remote I/O Master Unit...
Page 240: Instruction Execution Times
Instruction Execution Times Section 6-3 The basic peripheral device and Link Unit servicing time would be 1.5 ms x 4, or 6 ms, for the Programming Console, Host Link Unit, and two PC Link Units. The total output refreshing and Unit servicing time computed above is thus 0.8 ms + 0.04 ms + 1.24 ms + 6 ms = 8.08 ms.
Page 241 Instruction Execution Times Section 6-3 µ µ Instruction Conditions ON execution time ( OFF execution time ( C1000H C2000H C1000H C2000H Constant for SV JMP: *DM for SV JMP: JMP: Constant for SV JMP: *DM for SV JMP: JMP: NOP(00) END(01) IL(02) ILC(03)
Page 242 Instruction Execution Times Section 6-3 µ µ Instruction Conditions ON execution time ( OFF execution time ( C1000H C2000H C1000H C2000H TIMH(15) Interrupt Constant for SV Normal cycle Interrupt *DM for SV JMP: Normal cycle JMP: JMP: WSFT(16) When shifting 1 word 36/38 24/26 When shifting 4,096 words using *DM...
Page 243 Instruction Execution Times Section 6-3 µ µ Instruction Conditions ON execution time ( OFF execution time ( C1000H C2000H C1000H C2000H Constant AND word → word ANDW(34) 19/21 13/14 *DM AND *DM → *DM 40/41 27/28 Constant OR word → word ORW(35) 19/20 13/14...
Page 244 Instruction Execution Times Section 6-3 µ µ Instruction Conditions ON execution time ( OFF execution time ( C1000H C2000H C1000H C2000H ÷ word → word DIVL(57) 192/194 128/129 Word ÷ *DM → *DM 210/212 140/141 BINL(58) When converting words to words 35/37 27/28 When converting *DM to *DM...
Page 245: Instruction Execution Times
Instruction Execution Times Section 6-3 µ µ Instruction Conditions ON execution time ( OFF execution time ( C1000H C2000H C1000H C2000H MOVB (82) When transferring word to a word 31/32 21/22 When transferring *DM to *DM 51/52 34/35 MOVD(83) When transferring word to a word 27/28 18/19 When transferring *DM to *DM...
Page 246: I/O Response Time
I/O Response Time Section 6-4 I/O Response Time The I/O response time is the time it takes for the PC to output a control signal after it has received an input signal. The time it takes to respond depends on the cycle time and when the CPU receives the input signal relative to the in- put refresh period.
Page 247 I/O Response Time Section 6-4 Overseeing Cycle time Cycle time Cycle Output refresh Input refresh Input CPU reads CPU writes signal input signal output signal Input ON delay Output ON delay Output signal I/O response time Maximum I/O response time = input ON delay + (cycle time x 2) + overseeing time + output ON delay Calculation Example The data in the following table would produce the minimum and maximum...
Page 248: Program Debugging And Execution
SECTION 7 Program Debugging and Execution This section provides the procedures for debugging a program and monitoring and controlling the PC through a Program- ming Console. If you are using a GPC, a FIT, or a computer running LSS, refer to the Operation Manual for procedures on these. Debugging .
Page 249: Debugging
Debugging Section 7-1 Debugging After inputting a program and correcting it for syntax errors, it must be exe- cuted and all execution errors must be eliminated. Execution errors include an excessively long cycle, errors in settings for various Units in the PC, and inappropriate control actions, i.e., the program not doing what it is designed to do.
Page 250: Entering Debug Mode
Debugging Section 7-1 Example The following displays show some of the messages that may appear. Refer to Section 8 Troubleshooting for an extensive list of error messages, their meanings, and the appropriate responses. Fatal errors Non-fatal errors All errors have been cleared 7-1-2 Entering Debug Mode...
Page 251: Address Execution
Debugging Section 7-1 When Debug mode is entered or left, data in the IR, AR, and LR areas is cleared unless the Data Retention control bit is ON (see 3-3-2 Data Reten- tion Control Bit) Key Sequence → (Program mode Debug mode) →...
Page 252 Debugging Section 7-1 Key Sequence Execution Address currently set Example Meaning of Displays Execution status 2 Execution status 1 Execution status 1 shows the execution condition of the current instruction or indicates that a block program is being executed. This status can be changed (set or reset) by using PLAY/SET or REC/RESET as long as B (see below) is not also being displayed.
Page 253: Debug Execution
Debugging Section 7-1 7-1-4 Debug Execution The Debug Execution operation is used to execute the program from the cur- rently displayed address to the address before the specified stop address. After switching from PROGRAM to Debug mode, read the program and set the address from which to start debugging.
Page 254: Address Tracing
Debugging Section 7-1 7-1-5 Address Tracing The Address Tracing operation is used to debug a section of 250 instructions and store the results in the Trace Memory. To set up the Address Tracing op- eration, press EXT and CHG, then specify a stop address, a trigger address, and a delay value (the address where tracing is to begin relative to the trigger address).
Page 255: Address Trace Read
Debugging Section 7-1 Example Previously set stop address Start address Previously set trigger address Previously set delay Use the NOT key to switch between + and –. Indicates number of execution loops when trigger address is not found before the stop address or END(01) instruction.
Page 256 Debugging Section 7-1 Key Sequence Example Meaning of Displays Address Read direction (+/–) Address relative to the trigger address Within an IL/ILC block Within a JMP/JME block NP: Block program not executed 0: OFF 1: ON B: Block program execution...
Page 257: Monitoring Operation And Modifying Data
Monitoring Operation and Modifying Data Section 7-2 Monitoring Operation and Modifying Data The simplest form of operation monitoring is to display the address whose operand bit status is to be monitored using the Program Read or one of the search operations. As long as the operation is performed in RUN or MONI- TOR mode, the status of any bit displayed will be indicated.
Page 258 Monitoring Operation and Modifying Data Section 7-2 LD and OUT can be used only to designate the first address to be displayed; they cannot be used when an address is already being monitored. Key Sequence Clears leftmost address Cancels monitor operation Examples The following examples show various applications of this monitor operation.
Page 259 Monitoring Operation and Modifying Data Section 7-2 Bit Monitor Word Monitor...
Page 260: Force Set/Reset
Monitoring Operation and Modifying Data Section 7-2 Multiple Address Monitoring Cancels monitoring of leftmost address Cancels Monitor operation 7-2-2 Force Set/Reset When the Bit/Word Monitor operation is being performed and a bit, timer, or counter address is leftmost on the display, PLAY/SET can be pressed to turn ON the bit, start the timer, or increment the counter and REC/RESET can be pressed to turn OFF the bit or reset the timer or counter.
Page 261 Monitoring Operation and Modifying Data Section 7-2 Key Sequence Example The following example shows how either bits or timers can be controlled with the Force Set/Reset operation. The displays shown below are for the follow- ing program section. 00002 TIM 000 #0123 012.3 s TIM 000...
Page 262: Hexadecimal/Bcd Data Modification
Monitoring Operation and Modifying Data Section 7-2 00100 ON (i.e., timer starts operation, turning OFF 00500, which is turned back ON when the timer has finished counting down the SV). (This example is in MONITOR mode.) Monitoring 00100 and 00500. Indicates that force set/reset is in progress.
Page 263: Hex/Ascii Display Change
Monitoring Operation and Modifying Data Section 7-2 Key Sequence Word currently monitored on [ Data ] left of display. Example The following example shows the effects of changing the PV of a timer. This example is in MONITOR mode Timing PV changed Timing Timing...
Page 264: Three-Word Monitor
Monitoring Operation and Modifying Data Section 7-2 Example 7-2-5 Three-word Monitor To monitor three consecutive words together, specify the lowest numbered word, press MONTR, and then press EXT to display the data contents of the specified word and the two words that follow it. A CLR entry changes the three-word monitor operation to a single-word dis- play.
Page 265: Three-Word Data Modification
Monitoring Operation and Modifying Data Section 7-2 Example 7-2-6 Three-word Data Modification This operation changes the contents of a word during the 3-word Monitor op- eration. The blinking square indicates where the data can be changed. After the new data value is keyed in, pressing WRITE causes the original data to be overwritten with the new data.
Page 266: Binary Monitor
Monitoring Operation and Modifying Data Section 7-2 Example 3-word Monitor in progress. Stops in the middle of monitoring. Resumes previous monitoring. 7-2-7 Binary Monitor You can specify that the contents of a monitored word be displayed in binary by pressing SHIFT and MONTR after the word address has been input. Words can be successively monitored by using the up and down keys to in- crement and decrement the displayed word address.
Page 267: Binary Data Modification
Monitoring Operation and Modifying Data Section 7-2 Example 7-2-8 Binary Data Modification This operation assigns a new 16-digit binary value to an IR, HR, AR, LR, or DM word. The cursor, which can be shifted to the left with the up key and to the right with the down key, indicates the position of the bit that can be changed.
Page 268: Changing Timer/Counter Sv
Monitoring Operation and Modifying Data Section 7-2 Example IR bit 00115 IR bit 00100 7-2-9 Changing Timer/Counter SV There are two ways to change the SV of a timer or counter. It can be done either by inputting a new value; or by incrementing or decrementing the cur- rent SV.
Page 269 Monitoring Operation and Modifying Data Section 7-2 Key Sequence Timer/Counter currently displayed Example The following examples show inputting a new constant, changing from a con- stant to an address, and incrementing to a new constant. Inputting New SV and Changing to Word Designation...
Page 270 Monitoring Operation and Modifying Data Section 7-2 Incrementing and Decrementing Current SV (during change operation) SV before the change Returns to original display with new SV...
Page 271: File Memory Operations
File Memory Operations Section 7-3 File Memory Operations When a File Memory Unit is connected to the PC, contents of the Program Memory and data areas can be transferred to and from the File Memory (FM) area. The FM area can thus be used for auxiliary program memory (UM) and data memory (IOM) storage, as well as for comment memory storage (CM) for ladder logic program comments.
Page 272: File Memory Write
File Memory Operations Section 7-3 Example Partial clear Clear all Last block number 7-3-2 File Memory Write The File Memory Write operation writes data to the FM area. Data either from program memory or a data area can be transferred to the FM area with this operation.
Page 273 File Memory Operations Section 7-3 transfer from the DM area, you must specify the number of blocks to be transferred. Key Sequence [ Start address ] [ Start block ] [ Start DM Wd ] [ No. of blocks ] [ Start block ] [ Start Wd ] (AR)
Page 274 File Memory Operations Section 7-3 Example For program memory Changing numbers Aborting during operation For a data area (here, DM) continued on next page...
Page 275: File Memory Verify
File Memory Operations Section 7-3 Continued from previous page. Changing numbers Aborting during operation 7-3-3 File Memory Verify The File Memory Verify operation compares data either in program memory or in a data area with data stored in the FM area. If the two sets of data differ, a ”VER ERR”...
Page 276 File Memory Operations Section 7-3 Example For program memory Changing numbers Aborting during operation For a data area (here, DM) continued on next page...
Page 277: File Memory Read
File Memory Operations Section 7-3 Continued from previous page. Changing numbers Aborting during operation 7-3-4 File Memory Read The File Memory Read operation is used to read user program data (UM) stored in the FM area and transfer it to a specified area in RAM Program Memory, or to read user data (IOM) in the FM area and transfer it to one of the CPU data areas.
Page 278 File Memory Operations Section 7-3 Key Sequence [ Start address ] [ Start block ] [ Start DM Wd ] [ No. of blocks ] [ Start block ] [ Start Wd ] (AR)
Page 279 File Memory Operations Section 7-3 Example For program memory Changing numbers Aborting during operation For a data area (here, DM) continued on next page...
Page 280: File Memory Edit
File Memory Operations Section 7-3 Continued from previous page. Changing numbers Aborting during operation 7-3-5 File Memory Edit The File Memory Edit operation allows you to read and modify data stored in the FM area (IOM). Data can be read in RUN mode with this function, but it can be modified only when in MONITOR or PROGRAM mode.
Page 281: Program Backup And Restore Operations
Program Backup and Restore Operations Section 7-4 Example Reading block #7 I/O memory Word Data contents Type of memory (** indicates empty area) Changing data contents from 1234 to 0005 Changing the word Read IR 009 Reading the program or comment data User program Comments Program Backup and Restore Operations...
Page 282: Saving Program Memory Data
Program Backup and Restore Operations Section 7-4 Be sure to clearly label all cassette tapes. Use patch cords to connect the cassette recorder earphone (or LINE-OUT) jack to the Programming Console EAR jack and the cassette recorder micro- phone (or LINE-IN) jack to the Programming Console MIC jack. Set the cas- sette recorder volume and frequency equalizer controls to maximum levels.
Page 283: Restoring Or Comparing Program Memory Data
Program Backup and Restore Operations Section 7-4 Example Selecting Program Memory Starting address of data to be recorded Last address Stop address specified Start recording Continue within 5 seconds Blinking Recording in progress When it comes to END Stop recording with CLR Saved up to stop address 7-4-2 Restoring or Comparing Program Memory Data...
Page 284 Program Backup and Restore Operations Section 7-4 Specify the start address for the data that is to be restored or compared. Start playing the cassette tape. Within 5 seconds, press SHIFT and PLAY/SET to restore data or VER to compare data. Program restoration or comparison continues until END(01) is reached or until the tape is finished, at which time the program size in Kwords is dis- played.
Page 285: Saving, Restoring, And Comparing Dm Data
Program Backup and Restore Operations Section 7-4 Example Restoring in progress Comparison in progress END reached END reached Stop restoring using CLR Stop comparison using CLR Restored up to END Compared up to end of tape 7-4-3 Saving, Restoring, and Comparing DM Data The procedures for saving, restoring and comparing DM area data are identi- cal to those for Program Memory except that the DM area is specified and start and stop addresses are not required.
Page 286 Program Backup and Restore Operations Section 7-4 Key Sequence Within 5 seconds Start Saving [ File no. ] recording Start Restoring playing Comparing Example: Saving DM Data Selecting the DM area Start recording Wait about 5 seconds Recording in progress Recording stopped using CLR key.
Page 287 Program Backup and Restore Operations Section 7-4 Example: Comparing DM Data Selecting the DM area Start tape playback Within 5 seconds Blinking Comparison in progress Stopped verification using CLR Key Verification stopped at the end.
Page 288 Program Backup and Restore Operations Section 7-4 Example: Restoring DM Data Selecting the DM area Start tape playback Within 5 seconds Blinking Restoring in progress Restoring stopped using CLR key. Restoring stopped at the end.
Page 289 Program Backup and Restore Operations Section 7-4 Example: Comparing DM Data Selecting the DM area Start tape playback Within 5 seconds Blinking Comparison in progress Stopped verification using CLR Key Verification stopped at the end.
Page 290: Error Processing
SECTION 8 Error Processing The C1000H and C2000H provide self-diagnostic functions to identify many types of abnormal system conditions. These functions minimize downtime and enable quick, smooth error correction. This section provides information on hardware and software errors that occur during PC operation. Program input and program syntax errors are described in Section 4 Writing and Inputting the Program.
Page 291: Alarm Indicators
Error Messages Section 8-4 Alarm Indicators There are two indicators on the front of the CPU that provide visual indication of an abnormality in the PC. The error indicator (ERR) indicates fatal errors (i.e., ones that will stop PC operation); the alarm indicator (ALARM) indicates nonfatal ones.
Page 292 Error Messages Section 8-4 Most of these are also indicated by FAL number being transferred to the FAL area of the SR area. The type of error can be quickly determined from the indicators on the CPU, as described below for the three types of errors. If the status of an indicator is not mentioned in the description, it makes no difference whether it is lit or not.
Page 293 Error Messages Section 8-4 Error and message FAL no. Probable cause Possible correction Duplex system error Error has occurred in Check Duplex System settings. Duplex System operation. Battery error Backup battery is Check battery and replace if missing or its voltage necessary.
Page 294: Error Flags
Error Messages Section 8-5 Error and message FAL no. Probable cause Possible correction Input-output I/O table error Input and output word Check the I/O table with I/O Table designations registered Verification operation and check all in I/O table do no agree Units to see that they are in with input/output words correct configuration.
Page 295: Troubleshooting
Troubleshooting Section 8-6 AR Area Address(es) Function 1901 FM Data Transfer Flag 1903 FM Blocks Different Error Flag 1904 FM Write-protected Error Flag 1905 Unsuccessful FM Write Flag 1906 FM Checksum Error Flag 1907 File Memory Unit Low Battery Flag 2400 to 2403 Leftmost digit of FALS-generating address (AR 25 contains the other four digits)
Page 296 Troubleshooting Section 8-6 Input Units Symptom Possible cause Correction All inputs do not turn ON, and External input voltage is not supplied. Supply power. i di indicators do not light. t li ht External input voltage is low. Raise supply voltage. Terminal screws are loose.
Page 297 Troubleshooting Section 8-6 Output Units Symptom Possible cause Correction All Outputs do not turn ON. Power is not supplied to loads. Supply power. Raise supply voltage. Terminal screws are loose. Tighten terminal screws. Faulty contact of terminal block Replace terminal block connector. connector Fuse is blown.
Page 298: Standard Models
Appendix A Standard Models CPU Backplane Name Remarks Model Backplane C1000H 9 I/O slots (see note) 6 Link slots C500-BC091 8 I/O slots 3 Link slots 3G2A5-BC081 5 Link slots C500-BC082 6 I/O slots 5 Link slots C500-BC061 5 I/O slots 3 Link slots 3G2A5-BC051 5 Link slots...
Page 299 Standard Models Appendix A Expansion I/O Backplane Name Remarks Model Expansion I/O Backplane For C2000H, 8 slots, w/I/O on-line exchange function 3G2C5-BI083 8 slots 3G2A5-BI081 5 slots 3G2A5-BI051 Power Supply 100 to 120/200 to 240 VAC (selectable) Output: 7 A 5 VDC 3G2A5-PS222-E 24 VDC Output: 7 A 5 VDC...
Page 300 Standard Models Appendix A I/O Units Name Remarks Model Input Unit 16 mA 5 to 12 VDC, 8 points/common, 2 circuits 16 pts 3G2A5-ID112 10 mA 12 to 24 VDC, 8 points/common, 2 circuits 16 pts 3G2A5-ID213 10 mA 12 to 24 VDC, ON response time: 15 ms max.
Page 301 Standard Models Appendix A Special I/O Units Name Remarks Model A/D Conversion Input 4 to 20 mA 1 to 5 V 2 pts 3G2A5-AD001 0 to 10 V 2 pts 3G2A5-AD002 0 to 5 V 2 pts 3G2A5-AD003 –10 to 10 V 2 pts 3G2A5-AD004 –5 to 5 V...
Page 302 Standard Models Appendix A Name Remarks Model ID Sensor C500-IDS01-V2 For long distance (3G2A5-ID02-E is required) C500-IDS02-V1 ID Adapter C500-IDA02 R/W Head V600-H06 Data Carrier V600-D2KR01 Link Units and Remote I/O Units Name Remarks Model Host Link Rack- APF/PCF 3G2A5-LK101-PEV1 mounting 3G2A5-LK101-EV1 RS-232C/RS-422...
Page 303 Standard Models Appendix A Link Units and Remote I/O Units (Continued) Name Remarks Model Optical Transmitting I/O DC Input No-voltage 8 pts APF/PCF 3G5A2-ID001-PE contact, 100 VAC 3G5A2-ID001-E AC/DC Input 12 to 24 VAC/DC 8 pts APF/PCF 3G5A2-IM211-PE 100 VAC 3G5A2-IM211-E AC Input 100 VAC...
Page 304 Standard Models Appendix A Plastic-Clad Optical Fiber Cable (PCF) Name Remarks Model Optical Fiber Cable (indoor) 0.1 m, w/connector Ambient temperature: –10°C to 70°C 3G5A2-OF011 1 m, w/connector 3G5A2-OF101 2 m, w/connector 3G5A2-OF201 3 m, w/connector 3G5A2-OF301 5 m, w/connector 3G5A2-OF501 10 m, w/connector 3G5A2-OF111...
Page 305 Standard Models Appendix A Optical Connectors Name Model SYSMAC NET: CV500-SNT31 S3200-COCF2011 SYSMAC LINK: CV500-SLK11, C1000H-SLK11 SYSMAC BUS/2: CV500-RM211/RT211 SYSMAC NET: C200H-SNT31 S3200-COCF2511 SYSMAC LINK: C200H-SLK11 SYSMAC NET: C500-SNT31-V4 S3200-COCH62M S3200-LSU03-01E/NSB11-E S3200-NSUA1-00E/NSUG4-00E FIT10-IF401 SYSMAC BUS: 3G2A5-RM001-(P)EV1 S3200-COCH82 3G2A5-RT001/RT002-(P)EV1 3G2A9-ALjj-(P)E SYSMAC NET Relay (M) Connector S3200-COCF62M SYSMAC NET Relay (F) Connector S3200-COCF62F...
Page 306 Standard Models Appendix A Peripheral Devices Name Remarks Model Programming Console Vertical, w/backlight 3G2A5-PRO13-E Horizontal, w/backlight 3G2A6-PRO15-E Programming Console For connecting Programming Console, GPC, or FIT. 3G2A2-CN221 Connecting Cable (Only use CN221 [2 m] for Programming Console.) C500-CN523 10 m C500-CN131 20 m C500-CN231...
Page 307 Standard Models Appendix A Optional Products Name Remarks Model Battery 3G2A9-BAT08 Relay 24 VDC G6B-1174P-FD-US-M I/O Terminal Cover For 38-pin block, special type 3G2A5-COV11 For 38-pin block, standard C500-COV12 For 20-pin block, standard C500-COV13 Connector Cover For I/O connector 3G2A5-COV01 For Link connector 3G2A5-COV02 For I/O Control Unit / I/O Interface Unit connector...
Page 308: Programming Instructions
Appendix B Programming Instructions A PC instruction is input either by inputting the corresponding Programming Console key(s) (e.g., LD, AND, OR, NOT) or by using function codes. To input an instruction via its function code, press FUN, the function code, and then WRITE. If the function code is in pointed parentheses <like this>, then SHIFT must be pressed before the above sequence.
Page 309 Appendix B Programming Instructions Function Code Name Mnemonic Page ROTATE RIGHT COMPLEMENT BCD ADD BCD SUBTRACT BCD MULTIPLY BCD DIVIDE AND WORD ANDW OR WORD EXCLUSIVE OR XORW EXCLUSIVE NOR XNRW INCREMENT DECREMENT SET CARRY CLEAR CARRY FILE MEMORY READ FILR FILE MEMORY WRITE FILW...
Page 310 Appendix B Programming Instructions Function Code Name Mnemonic Page REVERSIBLE SHIFT REGISTER SFTR TABLE COMPARE TCMP ASCII CONVERT I/O WRITE WRIT I/O READ READ INTERRUPT CONTROL NETWORK SEND SEND SUBROUTINE ENTRY SUBROUTINE DEFINE RETURN WATCHDOG TIMER REFRESH BLOCK PROGRAM BEGIN BPRG I/O REFRESH IORF...
Page 311 Appendix B Instruction Execution Times Table: Instruction Execution Times µ µ Instruction Conditions ON execution time ( OFF execution time ( C1000H C2000H C1000H C2000H LD NOT AND NOT OR NOT AND LD OR LD OUT NOT Constant for SV *DM for SV R: 29 R: 19...
Page 312 Appendix B Instruction Execution Times µ µ Instruction Conditions ON execution time ( OFF execution time ( C1000H C2000H C1000H C2000H CNTR(12) Constant for SV R: 15 R: 10 IL: 10 IL: 7 *DM for SV JMP: 10 JMP: 7 DIFU(13) Normal: 15 Normal: 10...
Page 313 Appendix B Instruction Execution Times µ µ Instruction Conditions ON execution time ( OFF execution time ( C1000H C2000H C1000H C2000H Constant + word → word ADD(30) 33/35 22/23 *DM + *DM → *DM 53/55 35/36 Constant + word → word SUB(31) 33/34 22/23...
Page 314 Appendix B Instruction Execution Times µ µ Instruction Conditions ON execution time ( OFF execution time ( C1000H C2000H C1000H C2000H ÷ constant → word DVB(53) 51/52 34/35 Word ÷ *DM → *DM 71/73 47/48 Word + word → word ADDL(54) 74/76 49/50...
Page 315 Appendix B Instruction Execution Times µ µ Instruction Conditions ON execution time ( OFF execution time ( C1000H C2000H C1000H C2000H ÷ word → word (equals 0) FDIV(79) 52/54 35/36 Word ÷ word → word (doesn’t equal 0) 174/175 116/117 Word ÷...
Page 316 Basic Instructions Appendix B Programming Instructions The following tables detail all of the ladder diagram programming instructions for the C1000H/C2000H PCs, and the applicable data areas for each. Bit and word addresses for each area are given in the footnotes at the bottom of the page.
Page 317 Basic Instructions Appendix B Name and Symbol Function Operand Data Page Mnemonic Areas Logically ORs the status of the designated bit with the current execution condition. OR LOAD Logically ORs the resultant execution None OR LD conditions of the preceding logic blocks. OR NOT Logically inverse...
Page 318 Special Instructions Appendix B Special Instructions Name Mnemonic Function Operand Data Page Symbol Areas NO OPERATION Nothing is executed and program None None NOP(00) operation moves to the next instruction. Required at the end of each program. None END(01) Instructions located after END(01) will not END(01) be executed.
Page 319 Special Instructions Appendix B Name Mnemonic Function Operand Data Page Symbol Areas STEP START Used with a control bit (B) to indicate the SNXT(09) end of the step, reset the step, and start the next step which has been defined SNXT(09) B with the same control bit.
Page 320 Special Instructions Appendix B Name Mnemonic Function Operand Data Page Symbol Areas MOVE Transfers data from source word, (S) to (@)MOV(21) destination word (D). MOV(21) MOVE NOT Transfers the inverse of the data in the (@)MVN(22) source word (S) to destination word (D). MVN(22) BCD TO BINARY Converts 4-digit, BCD data in source word...
Page 321 Special Instructions Appendix B Name Mnemonic Function Operand Data Page Symbol Areas ROTATE LEFT Each bit within a single word of data (Wd) (@)ROL(27) is moved one bit to the left, with bit 15 moving to carry (CY), and CY moving to bit ROL(27) ROTATE RIGHT Each bit within a single word of data (Wd)
Page 322 Special Instructions Appendix B Name Mnemonic Function Operand Data Page Symbol Areas BCD DIVIDE Divides the 4-digit BCD dividend (Dd) by (@)DIV(33) the 4-digit BCD divisor (Dr), and outputs the result to the specified result words. R DIV(33) receives the quotient; R + 1 receives the remainder.
Page 323 Special Instructions Appendix B Name Mnemonic Function Operand Data Page Symbol Areas SET CARRY Sets the Carry Flag (i.e., turns CY ON). None STC(40) (@)STC(40) CLEAR CARRY Clears the Carry Flag (i.e, turns CY None CLC(41) (@)CLC(41) OFF). FILE MEMORY READ Reads data from the File Memory area in N/S: (@)FILR(42)
Page 324 Special Instructions Appendix B Name Mnemonic Function Operand Data Page Symbol Areas TRACE MEMORY Initiates data tracing. Used in conjunction None SAMPLE with flags in the AR area to simplify TRSM(45) debugging. Parameters are set using the Address Trace operation on a Programming Console or other System Support Tool (e.g., FIT, GPC, or LSS).
Page 325 Special Instructions Appendix B Name Mnemonic Function Operand Data Page Symbol Areas BINARY MULTIPLY Multiplies 4-digit hexadecimal (@)MLB(52) multiplicand (Md) and 4-digit multiplier (Mr), and outputs the 8-digit hexadecimal result to the specified result words (R and R+1). R and R+1 must be in the same data MLB(52) area.
Page 326 Special Instructions Appendix B Name Mnemonic Function Operand Data Page Symbol Areas DOUBLE BCD Multiplies the 8-digit BCD multiplicand and MULTIPLY 8-digit BCD multiplier, and outputs the (@)MULL(56) result to the specified result words. All words for any one operand must be in the same data area.
Page 327 Special Instructions Appendix B Name Mnemonic Function Operand Data Page Symbol Areas BIT COUNTER Counts the number of ON bits in one or (@)BCNT(67) more words (SB is the beginning source BCNT(67) word) and outputs the result to the specified result word (R). N gives the number of words to be counted.
Page 328 Special Instructions Appendix B Name Mnemonic Function Operand Data Page Symbol Areas SQUARE ROOT Computes the square root of an 8-digit (@)ROOT(72) BCD value (Sq and Sq + 1) and outputs the truncated 4-digit, integer result to the specified result word (R). Sq and Sq + 1 ROOT(72) must be in the same data area.
Page 329 Special Instructions Appendix B Name Mnemonic Function Operand Data Page Symbol Areas 4-TO-16 DECODER Converts up to four hexadecimal digits in (@)MLPX(76) the source word (S), into decimal values from 0 to 15, and turns ON the corresponding bit(s) in the result word(s) (R).
Page 330 Special Instructions Appendix B Name Mnemonic Function Operand Data Page Symbol Areas FLOATING POINT Divides one floating point value by another DIVIDE and outputs a floating point result. The (@)FDIV(79) rightmost seven digits of each set of two words (eight digits) are used for mantissa, and the leftmost digit is used for the exponent and its sign (Bits 12 to 14 give the FDIV(79)
Page 331 Special Instructions Appendix B Name Mnemonic Function Operand Data Page Symbol Areas MOVE DIGIT Moves hexadecimal content of up to four (@)MOVD(83) specified 4-bit source digit(s) from the source word to the specified destination digit(s) (S gives the source word address. D specifies the destination word).
Page 332 Special Instructions Appendix B Name Mnemonic Function Operand Data Page Symbol Areas TABLE COMPARE Compares a 4-digit hexadecimal value TB/R: (@)TCMP(85) (CD) with values in table consisting of 16 words (TB: is the first word of the comparison table). If the value of CD falls within any of the comparison ranges, corresponding bits in result word (R) are agreement,...
Page 333 Special Instructions Appendix B Name Mnemonic Function Operand Data Page Symbol Areas I/O READ READ(88) reads data from memory area of (@)READ(88) an Special I/O Unit and transfers it through word (S) allocated to the Special I/O Unit to destination words (D gives the address of the first destination word).
Page 334 Special Instructions Appendix B Name Mnemonic Function Operand Data Page Symbol Areas NETWORK SEND Transfers data from n source words (S is D/C: (@)SEND(90) the starting word) to the destination words (D is the first address) in node N of the specified network (in a SYSMAC LINK or NET Link System).
Page 335 Special Instructions Appendix B Name Mnemonic Function Operand Data Page Symbol Areas WATCHDOG TIMER Sets the maximum and minimum limits REFRESH for the watchdog timer (normally 0 to 130 0 to 63 (@)WDT(94) WDT(94) T ms). New limits: Maximum time = 130 + (100 x T) Minimum time = 130 + (100 x (T–1)) BLOCK PROGRAM Indicates the beginning of a block...
Page 336 Special Instructions Appendix B Name Mnemonic Function Operand Data Page Symbol Areas NETWORK RECEIVE Transfers data from the source words (S is C/D: (@)RECV(98) the first word) from node N of the specified network (in a SYSMAC LINK or NET Link System) to the destination words starting at D.
Page 337 Block Program Instructions Appendix B Block Program Instructions Name Mnemonic Symbol Function Operand Data Areas Page BLOCK PROGRAM END BEND<01> Indicates the end of a block program. None BEND<01> CONDITIONAL BRANCH IF<02> Indicates the part of the program that IF<02> is to be executed when a given IF<02>...
Page 338 Block Program Instructions Appendix B Name Mnemonic Symbol Function Operand Data Areas Page BLOCK PROGRAM BPRS<12> Restarts execution of the designated RESTART block program. 0 to 99 BPRS<12> N TIMER WAIT TIMW<13> The execution of the block program TIMW<13> N between the TIMW<13>...
Page 339: Programming Console Operations
Appendix C Programming Console Operations This Appendix provides a table which sums up the Programming Console operations. The table gives the op- eration name and the function it performs. Name Function Page Password Input Prompts the user for the access password. Buzzer ON/OFF Controls whether the buzzer will sound for keystroke inputs.
Page 340 Appendix C Programming Console Operations Name Function Page Cycle Time Display Measures the duration of the current cycle. Cycle times will vary according to the execution conditions which exist in each cycle. Hex-ASCII Converts 4-digit hexadecimal data in the DM area to ASCII and vice-versa. Display Change Binary Monitor Displays the monitored area in binary format.
Page 341 Appendix C Programming Console Operations System Operations The following table lists the Programming Console operations according to their function. A brief description of each operation is given, along with the allowable modes in which it can be implemented, and the keystroke sequence used to enter it.
Page 342 Appendix C Programming Console Operations Operation/Description Modes* Key sequence I/O Table Verify R P M Used to check that the registered I/O SHIFT Table matches actual arrangement of I/O Units. Pressing VER displays the next inconsistency. I/O Table Read R P M Used to read the I/O Table.
Page 343 Appendix C Programming Console Operations Programming Operations Operation/Description Modes* Key sequence Address Designation R P M Displays the specified address. Can [Address] be used to start programming from a non-zero address or to access an address for editing. Leading zeros need not be entered.
Page 344 Appendix C Programming Console Operations Operation/Description Modes* Key sequence Instruction Insert and [Enter new At the desired position Instruction Delete Insert in program: instruction] The displayed instruction can be deleted, or another instruction can be inserted before it. Care should be Instruction taken to avoid inadvertent deletions currently...
Page 345 Appendix C Programming Console Operations Debugging Operations Operation/Description Modes* Key sequence Debug Operation Enter MONTR Used to debug the program while in SHIFT Program Mode. Program Input, Program Clear, Instruction Insert, and Instruction Delete operations are Debug operation) (Program mode not available.
Page 346 Appendix C Programming Console Operations Monitoring and Data Changing Operations Operation/Description Modes* Key sequence Bit/Word Monitor R P M Up to six memory addresses, CONT containing either words or bits, or a [Address] SHIFT combination of the two, can be monitored at once.
Page 347 Appendix C Programming Console Operations Operation/Description Modes* Key sequence Binary Data Change Binary monitor in progress. This operation is used to change the value of IR, HR, AR, LR, or DM words WRITE Word currently displayed. bit-by-bit. The cursor can be moved left by using the up key, and right by using the down key.
Page 348 Appendix C Programming Console Operations Operation/Description Modes* Key sequence Hex-ASCII Display Change R P M Converts 4-digit hexadecimal DM Word currently data to ASCII and vice-versa. displayed Binary Monitor R P M The contents of a monitored word [Word address] can be specified to be displayed in binary by pressing SHIFT and MONTR after entering the word...
Page 349 Appendix C Programming Console Operations Cassette Tape Operations Operation/Description Modes* Key sequence Program Memory Save Copies data from the Program [Start address] [File no.] WRITE Memory to tape. The file no. specified in the instructions provides an identifying address information within the tape. Each file Start recording with the [Stop address] WRITE...
Page 350 Appendix C Programming Console Operations b) When restoring from tape or comparing data, the Programming Console needs to be ready to receive data before the data is transfered from the tape. File Memory Operations Operation/Description Modes* Key sequence File Memory Clear CONT Clears the FM area.
Page 351 Appendix C Programming Console Operations Operation/Description Modes* Key sequence File Memory Write CONT Writes data from the Program SHIFT Memory or specified data areas to the FM area. Data is written in blocks of 128 words. Program Memory When transferring data from the [Start UM address] [Start block] MONTR...
Page 352: Error And Arithmetic Flag Operation
Appendix D Error and Arithmetic Flag Operation The following table shows the instructions that affect the ER, CY, GT, LT and EQ flags. In general, ER indi- cates that operand data is not within requirements. CY indicates arithmetic or data shift results. GT indicates that a compared value is larger than some standard, LT that it is smaller, and EQ, that it is the same.
Page 353 Appendix D Error and Arithmetic Flag Operation Flags Instructions 25503(ER) 25504(CY) 25505(GR) 25506(EQ) 25507(LE) END(01) STEP(08) SNXT(09) CNTR(12) TIMH(15) WSFT(16) CMP(20) MOV(21) MVN(22) BIN(23) BCD(24) ASL(25) ASR(26) ROL(27) ROR(28) COM(29) ADD(30) SUB(31) MUL(32) DIV(33) ANDW(34) ORW(35) XORW(36) XNRW(37) INC(38) DEC(39) STC(40) CLC(41) FILR(42)
Page 354 Appendix D Error and Arithmetic Flag Operation Flags Instructions 25503(ER) 25504(CY) 25505(GR) 25506(EQ) 25507(LE) FILP(44) TRSM(45) MSG(46) ADB(50) SBB(51) MLB(52) DVB(53) ADDL(54) SUBL(55) MULL(56) DIVL(57) BINL(58) BCDL(59) FUN67 BCMP(68) XFER(70) BSET(71) ROOT(72) XCHG(73) SLD(74) SRD(75) MLPX(76) DMPX(77) SDEC(78) FDIV(79) DIST(80) COLL(81) MOVB(82) MOVD(83)
Page 355 Appendix D Error and Arithmetic Flag Operation Flags Instructions 25503(ER) 25504(CY) 25505(GR) 25506(EQ) 25507(LE) WRIT(87) READ(88) FUN89 SEND(90) SBS(91) SBN(92) RET(93) WDT(94) BPRG(96) IORF(97) RECV(98) BEND<01> IF<02> ELSE<03> IEND<04> WAIT<05> EXIT<06> SET<07> RSET<08> LOOP<09> LEND<10> BPPS<11> BPRS<12> TIMW<13> CNTW<14> TMHW<15> Note: means that the flag is affected by the result of instruction execution.
Page 356: Data Areas
Appendix E Data Areas The data areas in the C1000H and C2000H are summarized below. These are the same for both PCs unless specified. Only dedicated bits are shown specifically. The use of all other bits is determined either by the Sys- tem the PC is involved in, e.g., PC Link or SYSMAC LINK Systems use the LR area, or by the programmer, e.g., storage of data in the DM area.
Page 357 Appendix E Data Areas Dedicated Bits Most of the bits in the SR and AR area are dedicated for specific purposes. These are summarized in the fol- lowing tables. Refer to 3-4 SR Area and 3-5 AR Area for details. SR Area As a rule, SR area bits can be used only for the purposes for which they are dedicated.
Page 358 Appendix E Data Areas Word(s) Bit(s) Function 1-minute clock pulse bit 0.02-second clock pulse bit Step Flag 08 to 12 Duplex System flags 0.1-second clock pulse bit 0.2-second clock pulse bit 1.0-second clock pulse bit Instruction Execution Error (ER) Flag Carry (CY) Flag Greater Than (GR) Flag Equals (EQ) Flag...
Page 359 Appendix E Data Areas Word(s) Bit(s) Function File Memory Unit Error Reset Bit FM Data Transfer Flag FM Write/Read Flag FM Blocks Different Error Flag FM Write-protected Error Flag Unsuccessful FM Write Flag FM Checksum Error Flag File Memory Unit Low Battery Flag FM Blocks 0 to 249 Write-protect Bit FM Blocks 250 to 499 Write-protect Bit FM Blocks 500 to 749 Write-protect Bit...
Page 360: I/O Assignment Records Sheets
Appendix F I/O Assignment Records Sheets This appendix contains sheets that can be copied by the programmer to record I/O bit allocations and terminal assignments on the Racks, as well as details of work bits, data storage areas, timers, and counters.
Page 361 I/O Bits Appendix F I/O Assignment Records Sheets Programmer: Program: Date: Page: Word: Unit: Word: Unit: Field device Notes Field device Notes Word: Unit: Word: Unit: Field device Notes Field device Notes...
Page 362 Work Bits Appendix F I/O Assignment Records Sheets Programmer: Program: Date: Page: Area: Word: Area: Word: Usage Notes Usage Notes Area: Word: Area: Word: Usage Notes Usage Notes...
Page 363 Data Storage Appendix F I/O Assignment Records Sheets Programmer: Program: Date: Page: Word Contents Notes Word Contents Notes...
Page 364 Timers and Counters Appendix F I/O Assignment Records Sheets Programmer: Program: Date: Page: TC address T or C Set value Notes TC address T or C Set value Notes...
Page 365: Program Coding Sheet
Appendix G Program Coding Sheet The following page can be copied for use in coding ladder diagram programs. It is designed for flexibility, al- lowing the user to input all required addresses and instructions. When coding programs, be sure to specify all function codes for instructions and data areas (or # for constant) for operands.
Page 366 Appendix G Program Coding Sheet Programmer: Program: Date: Page: Address Instruction Operand(s) Address Instruction Operand(s)
Page 367 Appendix G Program Coding Sheet Programmer: Program: Date: Page: Address Instruction Operand(s) Address Instruction Operand(s)
Page 368: Data Conversion Table
Appendix H Data Conversion Table Decimal Binary 00000000 00000000 00000001 00000001 00000010 00000010 00000011 00000011 00000100 00000100 00000101 00000101 00000110 00000110 00000111 00000111 00001000 00001000 00001001 00001001 00010000 00001010 00010001 00001011 00010010 00001100 00010011 00001101 00010100 00001110 00010101 00001111 00010110 00010000 00010111 00010001...
Page 369: Extended Ascii
Appendix I Extended ASCII ASCII Codes Bits 0 to 3 Bits 4 to 7 0000 0001 0010 0011 0100 0101 0110 0111 1010 1011 1100 1101 1110 1111 0000 Space 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101...
Page 370: Glossary
Glossary address The location in memory where data is stored. For data areas, an address consists of a two-letter data area designation and a number that designates the word and/or bit location. For the UM area, an address designates the in- struction location (UM area).
Page 371 Glossary cial purposes, such as holding the status input from external devices, while other bits are available for general use in programming. bit address The location in memory where a bit of data is stored. A bit address must specify (sometimes by default) the data area and word that is being ad- dressed, as well as the number of the bit.
Page 372 Glossary condition An message placed in an instruction line to direct the way in which the termi- nal instructions, on the right side, are to be executed. Each condition is as- signed to a bit in memory that determines its status. The status of the bit as- signed to each condition determines, in turn, the execution condition for each instruction up to a terminal instruction on the right side of the ladder diagram.
Page 373 Glossary debug A process by which a draft program is corrected until it operates as intended. Debugging includes both the removal of syntax errors, as well as the fine-tuning of timing and coordination of control operations. decimal A number system where all numbers are expressed to the base 10. In a PC all data is ultimately stored in binary form, four binary bits are often used to represent one decimal digit, via a system called binary-coded decimal.
Page 374 Glossary Duplex System A C2000H PC System that uses a Duplex CPU. Duplex Unit The Unit that coordinates the CPU activities of a Duplex System. electrical noise Random variations of one or more electrical characteristics such as voltage, current, and data, which might interfere with the normal operation of a de- vice.
Page 375 Glossary flicker bit A bit that is programmed to turn ON and OFF at a specific frequency. floating point decimal A decimal number expressed as a number between 0 and 1 (the mantissa) multiplied by a power of 10, e.g., 0.538 x 10 Floppy Disk Interface Unit A Unit used to interface a floppy disk drive to a PC so that programs and/or data can be stored on floppy disks.
Page 376 Glossary initialization error An error that occurs either in hardware or software during the PC System startup, i.e., during initialization. initialize Part of the startup process whereby some memory areas are cleared, system setup is checked, and default values are set. input The signal coming from an external device into the PC.
Page 377 Glossary I/O Control Unit A Unit mounted to the CPU Rack in certain PCs to monitor and control I/O points on Expansion I/O Units. I/O devices The devices to which terminals on I/O Units or Special I/O Units, or other Units are connected.
Page 378 Glossary ladder diagram symbol A symbol used in a ladder-diagram program. ladder instruction An instruction that represents the ‘rung’ portion of a ladder-diagram program. The other instructions in a ladder diagram fall along the right side of the dia- gram and are called terminal instructions. Ladder Support Software A software package that provides most of the functions of the Factory Intelli- gent Terminal on an IBM AT, IBM XT, or compatible computer.
Page 379 One loop of a SYSMAC NET Link System (OMRON’s LAN) can consist of up to 126 nodes. Each node is occupied by a SYSMAC NET Link Unit mounted to a PC or a device providing an interface to a computer or other peripheral device.
Page 380 Glossary normally closed condition A condition that produces an ON execution condition when the bit assigned to it is OFF, and an OFF execution condition when the bit assigned to it is normally closed condition A condition that produces an ON execution condition when the bit assigned to it is ON, and an OFF execution condition when the bit assigned to it is OFF.
Page 381 Glossary A logic operation whereby the result is true if either of two premises is true, or if both are true. In ladder-diagram programming the premises are usually ON/ OFF states of bits or the logical combination of such states called execution conditions.
Page 382 Glossary port A connector on a PC or computer that serves as a connection to an external device. present value The current value registered in a device at any instant during its operation. Present value is abbreviated as PV. printed circuit board A board onto which electrical circuits are printed for mounting into a comput- er or electrical device.
Page 383 Glossary refresh The process of updating output status sent to external devices so that it agrees with the status of output bits held in memory and of updating input bits in memory so that they agree with the status of inputs from external de- vices.
Page 384 Glossary self-maintaining bit A bit that is programmed to maintain either an OFF or ON status until set or reset by specified conditions. servicing The process whereby the PC provides data to or receives data from external devices or remote I/O Units, or otherwise handles data transactions for Link Systems.
Page 385 Glossary Abbreviation for set value. switching capacity The maximum voltage/current that a relay can safely switch on and off. syntax error An error in the way in which a program is written. Syntax errors can include ‘spelling’ mistakes (i.e., a function code that does not exist), mistakes in specifying operands within acceptable parameters (e.g., specifying reserved SR bits as a destination), and mistakes in actual application of instructions (e.g., a call to a subroutine that does not exist).
Page 386 Unit In OMRON PC terminology, the word Unit is capitalized to indicate any prod- uct sold for a PC System. Though most of the names of these products end with the word Unit, not all do, e.g., a Remote Terminal is referred to in a col- lective sense as a Unit.
Page 387: Index
Index control bit Data Retention, 28 data tracing, 34 address, in data area, 17 definition, 16 File Memory, 34 address tracing. See tracing, data tracing. manipulating, 23 AR area, 31–36 Output OFF, 29 arithmetic flags, 103 Control System, definition, 3 controlled system, definition, 3 arithmetic operations, flags, 31 counters...
Page 388 Index data tracing, 211–214 control bits and flags, 34 Factory Intelligent Terminal. See peripheral devices debugging, 244–251 address trace read, 250–251 FAL area, 29, 208 address tracing, 249–250 FAL code, FALS-generating Address, 36 execution by instruction address, 246 execution from Programming Console, 248 fatal operating errors, 288 Programming Console debug operation, 245 File Memory, 39...
Page 389 Index BPPS<11>, 198 BPRG(96), 190 BPRS<12>, 198 I/O bit BSET(71), 136 definition, 18 CLC(41), 159 limits, 18 CMP(20), 142 CNT, 122 I/O points, refreshing, 211 CNTR(12), 125 I/O Rack, definition, 12 CNTW<14>, 196 COLL(81), 139 I/O refreshing, time required, 230 COM(29), 179 I/O response times, 241 DEC(39), 159...
Page 390 Index OR, 46, 108 combining with AND, 47 OR LD, 50, 109 jump numbers, 115 combining with AND LD, 51 jumps, 115–116 use in logic blocks, 51 OR NOT, 46, 108 ORW(35), 180 OUT, 48, 109 OUT NOT, 48, 109 ladder diagram READ(88), 218 branching, 86...
Page 391 Index program execution, 97 Program Memory, 39 backup and restore, 278–280 nesting, subroutines, 184 setting address and reading content, 75–76 non-fatal operating errors, 287 structure, 44 normally closed condition, definition, 43 programming backup onto cassette tape, 276–284 NOT, definition, 43 checks for syntax, 79–81 displaying and clearing error messages, 244 entering and editing, 76...
Page 392 Index subroutines, 182–189 TR area, 39 TR bits, use in branching, 86 accessing via TC area, 38 changing, 263 Trace Memory, 39 CNTR(12), 126 timers and counters, 117 tracing See also See data tracing and address tracing. SYSMAC LINK System address trace read, 250–251 Active Node Flags, 33 address tracing, 249–250...
Page 393: Revision History
Revision History A manual revision code appears as a suffix to the catalog number on the front cover of the manual. Cat. No. W140-E1-04 Revision code The following table outlines the changes made to the manual during each revision. Page numbers refer to the previous version.
Page 394 Wegalaan 67-69, NL-2132 JD Hoofddorp The Netherlands Tel: (31)2356-81-300/Fax: (31)2356-81-388 OMRON ELECTRONICS LLC 1 East Commerce Drive, Schaumburg, IL 60173 U.S.A. Tel: (1)847-843-7900/Fax: (1)847-843-8568 OMRON ASIA PACIFIC PTE. LTD. 83 Clemenceau Avenue, #11-01, UE Square, Singapore 239920 Tel: (65)6835-3011/Fax: (65)6835-2711...
Page 395 Authorized Distributor: Cat. No. W140-E1-04 Note: Specifications subject to change without notice. Printed in Japan...

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Sysmac c1000h

Omron SYSMAC C2000H Operation Manual

Table of Contents

Section 1 Introduction

Section 3 Memory Areas

Section 4 Writing and Inputting the Program

Section 5 Instruction Set

Section 6 Program Execution Timing

Section 7 Program Debugging and Execution

Program Debugging and Execution

Section 7

Error Processing

Glossary

Index

Revision History

Quick Links

Chapters

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Summary of Contents for Omron SYSMAC C2000H