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4.10
LCD/CVF SCHEMATIC DIAGRAM [GR-AX970U]
0 1 MAIN (LCD/CVF)
5
TO REG
REG_4.8V
REG_-15V
GND
C7054
4.7
/25
4
TO REG
REG+12V
REG_15V
REG_3.2V
Q7001
PUMX1-W
R-Y
3
R7086
R7088
12k
22k
TO DSP
R-Y
ROUT
Y
GOUT
B-Y
BOUT
TO CPU
VF_LCD
TO DSP
DAC_3.2V
R7077
12k
2
∗
∗
R7114
1
∗
NOTE : The parts with marked ( ) is not used.
A
B
C7061
4.7µ
Q7003
Q7005
PUMX1-W
PUMX1-W
R7101
C7062
10k
4.7µ
R7099
C7063
10k
4.7µ
B-Y
R7100
10k
R7093
R7096
R7098
R7091
22k
12k
22k
12k
∗
∗
IC7008
Q7011
Q7013
Q7015
∗
∗
∗
∗
C7064
∗
∗
R7118
R7122
∗
∗
∗
C7065
∗
C7066
∗
C
NOTES :
For the destination of each signal and further line connections that are cut off from
this diagram , refer to "4.1 BOARD INTERCONNECTIONS".
When ordering parts , be sure to order according to the Part Number indicated in the Parts List.
C7021
4.7
/25
T
C7022
0.01
∗
∗
∗
∗
∗
∗
C7052
∗
C7051
∗
∗
∗
∗
∗
∗
T
D
E
4-21
4-22
M2_MAIN_LCD/CVF_BLOCK
JVC_CVF_ONLY_MODEL
IC7005
BA4558F-X
C7041
10
/10
y10266001a_rev0
F
G
TO CPU
OPEN_SW
TO REG
GND
TO CPU
LCD_CTL
REG_4.8V
CN16
∗
OPEN
OPEN_SW
GND
GND
LCD_CTL
REG_4.8V
REG_4.8V
VSS
REG_15V
MREG_4.8
MONI_R
REG+12V
MONI_G
REG_3.2V
MONI_B
HDCVF
VDCVF
HRP1
DSP_REST
PMIRROR
GND
GND
GND
REV_SW
REV_SW
PMIRROR
TO CPU
DSP_REST
HRP1
TO DSP
VDCVF
HDCVF
H
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