Texas Instruments SLAU081 User Manual
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Texas Instruments SLAU081 User Manual

Texas Instruments SLAU081 User Manual

Texas instruments stereo amplifier user's guide slau081
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TLC4541 EVM
User's Guide
January 2002
AAP Data Acquisition (Dallas)
SLAU081

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  • Page 1 TLC4541 EVM User’s Guide January 2002 AAP Data Acquisition (Dallas) SLAU081...
  • Page 2 Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
  • Page 3 EVM IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not considered by TI to be fit for commercial use. As such, the goods being provided may not be complete in terms...
  • Page 4 EVM schematic located in the EVM User’s Guide. When placing measurement probes near these devices during operation, please be aware that these devices may be very warm to the touch. Copyright 2002, Texas Instruments Incorporated Mailing Address: Texas Instruments Post Office Box 655303...

  • Page 5: Table Of Contents

    Introduction ..............EVM Modes .
  • Page 6 Running Title—Attribute Reference Figures 2–1 SAM Configuration ............Tables 2–1 Default Switch Settings...

  • Page 7: Introduction

    This chapter contains an overview of the features and functions of the EVM. Topic EVM Modes ........... Analog Input Conditioning .

  • Page 8: Evm Modes

    EVM Modes This user’s guide has been written to help you get the most from your evaluation module (EVM). The TLC4541 EVM is a member of the multipurpose (MP) family of serial EVMs. It provides a platform to demonstrate the performance and functionality of the TLC4541 ADC and the TLV5636 DAC.

  • Page 9: Stand-Alone Mode

    1.1.1 Stand-Alone Mode A unique feature of this EVM is the facility it offers the user to closely couple the ADC and DAC with a minimum of user intervention. This feature allows the serial bit stream from the digitized analog output to be fed directly to the DAC. Therefore, the signal that is fed into the ADC can be reconstructed via the DAC.

  • Page 10: Getting Started

    This chapter describes how the user can modify the various options of this EVM. Topic Shipping (Default Configuration) Jumpers ........... . . Switches .

  • Page 11: Shipping (Default Configuration)

    Shipping (Default Configuration) It is very important that users feel comfortable with the EVM from the beginning. To achieve this, each unit is manufactured and shipped in a predetermined condition. This allows the user to begin evaluation of the system immediately and to have confidence that the EVM is working. To confirm that the EVM is working properly, follow the steps below: 1) Apply power to the system.

  • Page 12: Default Switch Settings

    Table 2–1. Default Switch Settings SW1-1 SW1-2 SW1-3 SW1-4 Table 2–2. Default Jumper Settings Default Configuration Pins 1–2 Pins 2–3 Inserted Not inserted Not inserted Inserted Not inserted Inserted Not inserted Inserted Not populated Not populated Not populated Not populated Not inserted Inserted Not inserted...

  • Page 13: Jumpers

    Jumpers 2.2 Jumpers The table below lists the functions that users can reconfigure along with the shipping condition. Table 2–3. Jumper/Function Reference Function Channel 0 Analog input Analog output Disable onboard signal generator Voltage reference 3.3-V/5-V analog supply select Clock/timer routing 2.2.1 Analog I/O Signal Conditioning The TLC4541 supports various signal conditioning configurations.

  • Page 14: Channel 0 Analog Output

    2.2.3 Channel 0 Analog Output With a one-channel DAC installed, this signal is the primary analog output (output A). With a two-channel DAC installed, the pinout of these devices effectively resolves this channel to be the secondary analog output (output B). Analog Input Configuration Channel 0 Reference Designator...

  • Page 15: Clock/Timer Routing

    Switches 2.2.7 Clock/Timer Routing A variety of options are available to the user. Be careful about altering these. Reference Designator This jumper defines the clock that the ADC and DAC use for all their timing. The user can select either the output from W23 or the output from W22 to be the base clock for the system. This jumper allows the user to select either an external clock, or the onboard 20-MHz oscillator for conversion.

  • Page 16: Connectors

    If SW1-1 is set to the on position, user mode is selected. In this case the user has absolute control of the data and control signals for the ADC and DAC. With SW1-1 in the on position, the logic that generates the control for SAM is disabled and plays no active part in the process.

  • Page 17: Connectors

    Connectors Reference Designator Description Analog input option, 26-pin DIL header Reference Designator Analog output for one-channel DAC Number Function Channel 0 input AGND Channel 1 input AGND Not connected AGND Not connected AGND Not connected AGND Not connected AGND Not connected AGND Not connected AGND...
  • Page 18 Reference Designator Description EVM power Analog output option, 26-pin DIL header Number Function –12 V 12 V No output AGND Analog output for one-channel DAC AGND Not connected AGND Not connected AGND Not connected AGND Not connected AGND Not connected AGND Not connected AGND...
  • Page 19 Connectors Reference Designator Description Number Analog input option for universal operational-amplifier operational-amplifier evaluation board, SIL evaluation board, SIL PTH not installed. 2-10 Function Noninverting input signal to dual operational amplifier, (2) Noninverting input signal to dual operational amplifier, (2) Inverting input signal to dual operational amplifier, (2) Inverting input signal to dual operational amplifier, (2) Nonfiltered output from dual operational amplifier, (2) Filtered output from dual operational amplifier, (2)

  • Page 20: Adc And Dac Direct Access

    2.6 Host Communication There are two ways to connect a host system (DSP/microprocessor): Texas Instruments’ new DSKs provide two dedicated 80-pin connectors. The EVM can be plugged directly onto these DSKs. This connector standard is referred to as the common connector.

  • Page 21: Common Connector

    Host Communication 2.6.1 Common Connector Reference Designator 80-pin memory interface connector for ’C5000 and ’C6000 DSK EVMs. Pins unused by this EVM are omitted for clarity. 2-12 Description Function Number PCI ground PCI ground PCI ground PCI ground PCI ground PCI ground 3.3 V 3.3 V...
  • Page 22 Reference Designator 80-pin peripheral and control connector for ’C5000 and ’C6000 DSK EVMs. Pins unused by this EVM are omitted for clarity. Description Host Communication Number Function 12 V –12 V PCI ground PCI ground PCI ground PCI ground CLKX PCI ground PCI ground CLKR...

  • Page 23: Legacy Connector

    Host Communication 2.6.2 Legacy Connector J12, J13, and J15 are three 2x20 headers daisy-chained together and are collectively referred to as the legacy connector. The principle behind this arrangement is to eliminate the confused and untidy custom cabling that is typically present when connecting a legacy DSP to an EVM.
  • Page 24 Consider a host cable signal assignment as shown below: Host Connector Pin No. Signal Pin No. Signal DGND DGND CLKX CLKR TOUT DGND DGND DGND CLKS The host connector mates with J12. Signals on either side of J12 are available on J13 and J15.
  • Page 25 Host Communication For clarity, the above table can be redrawn with J12 removed. Pin No. The table below shows the signal names and pin assignments that the composite connector shown above must be mapped onto. Pin No. Signal CLKX CLKR Resvd CLKS TOUT...
  • Page 26 All of the signals required to interface the EVM to the host are now available on either J13 or J15. This is simply a matter of wire-wrapping in the following way: Wire Wrap Pin No. Signal Pin No. CLKX TOUT Wire Wrap Pin No.
  • Page 27 Host Communication All of these connectors are shown below: Reference Designator 2-18 Description Number 20-pin connector Signal Name/Function J13 pin 2 J15 pin 1 J13 pin 4 J15 pin 3 J13 pin 6 J15 pin 5 J13 pin 8 J15 pin 7 J13 pin 10 J15 pin 9 J13 pin 12...
  • Page 28 Reference Designator Description 20-pin signal connector Host Communication Number Signal Name/Function ADC select signal J12 pin 1 CLKX/transmit clock J12 pin 3 CLKR receive clock J12 pin 5 DX/data transmit J12 pin 7 DR/data receive J12 pin 9 FSX/frame sync transmit J12 pin 11 FSR/frame sync receive J12 pin 13...
  • Page 29 Host Communication Reference Designator 2-20 Description Number 20-Pin connector Signal Name/Function J12 pin 2 DGND J12 pin 4 DGND J12 pin 6 DGND J12 pin 8 DGND J12 pin 10 DGND J12 pin 12 DGND J12 pin 14 DGND J12 pin 16 DGND J12 pin 18 DGND...

  • Page 30: Bill Of Materials, Board Layout, And Schematics

    Appendix A Bill of Materials, Board Layout, and Schematics This appendix contains the bill of materials, board layouts, and the EVM schematics. Bill of Materials, Board Layout, and Schematics...
  • Page 31 Input Config BNC_0 BNC_1 IDC_0 IDC_1 Channel_0 Channel_1 Power & Reference EXT_VREFP +Supply +Supply Ground Ground -Supply -Supply +5V_IN +5V_IN ADC_Data_out SENSE SENSE VREFP VREFP LCL_CS_ADC* LCL_CLKX In_0 In_1 LCL_CLKX LCL_CS_DAC* DAC_Data_in DAC_Write* VREFP AOUT AOUT_A VREFP VREFP SENSE SENSE PCI_+5v PCI_+12V PCI_GND...
  • Page 32 +Supply PCI_+12V Ground PCI_GND -Supply PCI_-12V +5V_IN PCI_+5v EXT_VREFP Power +VIN REF_IN -VIN FB13 +DVdd SM_FB_27--044447 Reference +VIN SENSE SENSE EXT_REFP 040500 + C11 + C57 10uF 10uF 10uF 10uF +DVdd +DVdd VREFP VREFP 12500 TI Boulevard. Dallas, Texas 75243 TITLE: Power &...
  • Page 33 +DVdd 4.7uF 0.1uF 0.01uF +VIN Green 0.1uF 10uF 4.7uF REF_IN -VIN BLM11A121SGPB 10uF TP16 +DVdd 0.1uF 10uF 10uF TP18 BLM11A121SGPB TPS77801D /ENA 357K 590K SENSE / FB 110K TP13 040500 TP12 BLM11A121SGPB 4.7uF 0.1uF 0.1uF 4.7uF TP11 12500 TI Boulevard. Dallas, Texas 75243 TITLE: Power Engineer:...
  • Page 34 VRE3050 +VIN +Vin 2.2uF SENSE Vout R50 5K TRIM 0.1uF + C38 2.2uF 040500 Not Installed 0.1uF TLE2081 Vout RV10 100K EXT_REFP 12500 TI Boulevard. Dallas, Texas 75243 TITLE: Reference Engineer: Joe Purvis DOCUMENT CONTROL #: Drawn By: Joe Purvis Reference DATE: 28-Nov-2001...
  • Page 35 SENSE VREFP 10uF 0.1uF AIN0 In_0 AIN or AIN0 or AIN(+) AIN1 SCLK or AIN1 or AIN(-) In_1 +AVdd 0.1uF 10uF 0.01uF ADC_REF ADC_REF AIN0 MSOP ADC AIN1 SOCKETED ADC 040500 Sr‰v†v‚ÃCv†‡‚…’ U501 +DVdd 100pF ADC_Data_out LCL_CLKX LCL_CS_ADC* 12500 TI Boulevard. Dallas, Texas 75243 TITLE: Engineer: Joe Purvis...
  • Page 36 AOUT A2_FLT A2_OUT B2_FLT B2_OUT AOUT_A DAC Out DAC_OUT OUT/OUTB VREF2 TP20 A204+ OUT/OUTB A203+ +AVdd A202- A201- A2/SD U801 DAC SOP(D) B2/SD B201- B202- B203+ B204+ DAC Out TP21 OUTA DAC_OUTA Sr‰v†v‚ÃCv†‡‚…’ +AVdd 040500 0.1uF 0.1uF 10uF 0.1uF SOCKETED DAC 12500 TI Boulevard.
  • Page 37 DAC_OUTA 4.7K DAC_OUT 4.7K RV11 100K 0.1uF TLE2081 Vout 0.1uF 100K 0.1uF Vout 0.1uF Sr‰v†v‚ÃCv†‡‚…’ 040500 OUTA OUT/OUTB 12500 TI Boulevard. Dallas, Texas 75243 TITLE: DAC Output Engineer: Joe Purvis DOCUMENT CONTROL #: 6430333 Drawn By: Joe Purvis Output conditioning DATE: 28-Nov-2001 FILE:...
  • Page 38 FB12 DSP_CLKX BLM11A121SGPB FB11 DSP_CLKR BLM11A121SGPB DSP_FSX BLM11A121SGPB DSP_FSR BLM11A121SGPB DSP_DX BLM11A121SGPB DSP_DR BLM11A121SGPB DSP_XF BLM11A121SGPB FB10 DSP_TOUT BLM11A121SGPB DSP_CLKS BLM11A121SGPB CLKX CLKR CLKS TOUT Memory Interface Connector CLKX CLKR +3.3v TOUT CLKS PCI_GND Peripheral & Control Connector 040500 PCI_-12V +3.3v PCI_+12V PCI_+5V...
  • Page 39 TO / FROM USER CONNECTIONS DSP_TOUT DSP_TOUT DSP_CLKS DSP_CLKS DSP_CLKX DSP_CLKX DSP_CLKR DSP_CLKR DSP_DX DSP_DX DSP_DR 0.01uF DSP_DR DSP_FSX DSP_FSX DSP_FSR DSP_FSR DSP_XF DSP_XF Stand Alone Mode LCL_CS_ADC* LCL_CS_ADC* LCL_CLKX LCL_CLKX ADC_Data_out ADC_Data_out TO / FROM ADC DAC_Data_in DAC_Data_in LCL_CS_DAC* LCL_CS_DAC* DAC_Write* DAC_Write*...
  • Page 40 U16B +DVdd 0.1uF U13B +DVdd 0.1uF U14B +DVdd 0.1uF U16A I12/O0/Q0 TP19 I13/O1/Q1 LCL_CS_DAC* I14/O2/Q2 LCL_CLKX I15/O3/Q3 ADC_Data_n3 I16/O4/Q4 I17/O5/Q5 I18/O6/Q6 I19/O7/Q7 ADC_Data_out I20/O8/Q8 TP17 I21/O9/Q9 CLK/I0 DAC_Write* U13A DSP_DR DSP_DR I12/O0/Q0 ADC_Data_n3 I13/O1/Q1 ADC_CS* ADC_Data_out LCL_CS_ADC* I14/O2/Q2 DAC_Data_in DSP_DX DAC_Data_in I15/O3/Q3 TP15...
  • Page 41 Signal Conditioning IN_0 OUT_0 BNC_0 IDC_0 BNC_1 IDC_1 Signal Conditioning IN_1 Prototype Area BB_Output_0 IN_0 B204+ B2_OUT B203+ B2_FLT B202- Signal Generator B201- Test signal 0 B2/SD A2/SD Test signal 1 A201- A202- A2_OUT A203+ A204+ A2_FLT VREF2 Prototype Area OUT_1 BB_Output_1 IN_1...
  • Page 42 0.1uF 10uF Duty adj. 49.9K Duty Adj. Sine Out 49.9K Sine Adj Sine Adj Square Out Timing Cap. FM Sweep Input FM Bias Triangle Out Not Connected Not connected V- / GND ICL8038 10uF 0.1uF 4.7K 100K 4.7K 0.1uF 4.7K 4.7K 100K 4.7K...
  • Page 43 IN_0 IN_1 BB_Output_0 BB_Output_1 Sr‰v†v‚ÃCv†‡‚…’ 040500 12500 TI Boulevard. Dallas, Texas 75243 TITLE: Prototype Area Engineer: Joe Purvis DOCUMENT CONTROL #: 6430333 Drawn By: Joe Purvis Prototype Area DATE: 28-Nov-2001 FILE: SIZE: REV: SHEET:...
  • Page 44 IN_1 0.1uF 0.1uF TLE2081 Vout 100K IN_0 0.1uF 040500 OUT_1 0.1uF TLE2081 Vout 12500 TI Boulevard. Dallas, Texas 75243 100K TITLE: Signal Conditioning Engineer: Joe Purvis DOCUMENT CONTROL #: 6430333 Drawn By: Joe Purvis Signal Conditioning DATE: 28-Nov-2001 FILE: Sr‰v†v‚ÃCv†‡‚…’ OUT_0 REV: SIZE:...

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