Mitsubishi MELSEC-Q Series Programming Manual page 71

(b) An index setting is applicable to both start I/O numbers of the intelligent function module
and buffer memory addresses for intelligent function module devices
EN
s
U10Z1\G0Z2
(c) An index setting is applicable to both network numbers and device numbers for link
*3
direct devices .
EN
s
J1Z1\K4X0Z2
(d) An index setting is applicable to both start I/O numbers of the CPU module and CPU
shared memory addresses for multiple CPU area devices
EN
s
U3E0Z1\G0Z2
*3: For intelligent function module devices and link direct devices, refer to the User's Manual (Function
Explanation, Program Fundamentals) of the CPU module to be used.
*4: For multiple CPU area devices, refer to the User's Manual (Function Explanation, Program Fundamentals) of
the CPU module to be used.
(e) A 32-bit index setting is applicable to extended data register (D) and extended link
register (W)
(for Universal model QCPU (excluding Q00UJCPU), and LCPU)
When applying an index setting to extended data registers (D) or extended link registers
(W), it can be applied in 32-bit range as applying an index setting to file registers (ZR) in
the following two methods.
• Specify a range of index registers used for a 32-bit index setting.
• Specify a 32-bit index setting using 'ZZ'.
32-bit index settings using 'ZZ' can be used for the following CPU modules only.
• QnU(D)(H)CPU with a serial number whose first five digits are '10042' or higher
(excluding Q00UJCPU)
• QnUDE(H)CPU
• LCPU
MOV
ENO
d
D0
If Z1=2 and Z2=8,
then U(10+2)\G(0+8)=U12\G8
MOV
ENO
d
D0
If Z1=2 and Z2=8,
then J(1+2)\K4X(0+8)=J3\K4X8
MOV
ENO
d
D0
*3
.
*4
.
4.6 Index Setting
4
4-49