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Version 3.0
SDB Interrupts
The SMT335E has been designed to allow transfers to be controlled by interrupt
conditions. The main constraint in the design was to make sure that only one
interrupt condition could be generated for each frame of data. This cannot be done
directly by mapping the FIFO flags to interrupt lines because the flags can generate
many edges during a transfer. Instead, after generating an interrupt condition, the
FPGA prevents the device from asserting further conditions until the last address of
the frame has been accessed.
Condition assertion during output:
1. Wait until the output FIFO has enough space to store a new frame, i.e.,
spaces available in the output FIFO >= OTRIGGER.
2. Assert a condition to synchronise a frame transfer (DSP to SDB).
3. Wait until the frame transfer has been completed before looking at the
available space again. Completion is detected by observing a write to the
FIFO at address:
SDB FIFO address + 4*(OTRIGGER–1)
Condition assertion during input:
1. Wait until the input FIFO contains at least one frame, i.e., words available
in the input FIFO >= ITRIGGER.
2. Assert a condition to synchronise a frame transfer (SDB to DSP).
3. Wait until the frame transfer has completed before looking at the number of
words available again. Completion is detected by observing a read from
the FIFO being performed at address:
SDB FIFO address + 4*(ITRIGGER-1)
Writing to IFLAGLEVEL or OFLAGLEVEL will allow the corresponding condition to be
reasserted even though a complete frame transfer may not have happened.
Page 24 of 53
SMT335E SMT375E User Manual
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