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EMIF Control Registers
The C6000 contains several registers that control the external memory interface
(EMIF). There is one global control register and a separate register for each of the
memory spaces CE0 to CE3. A full description of these registers can be found in the
C600001 Peripherals Reference Guide[1].
The standard bootstrap will initialise these registers to the following values:
GC (global control)
CE0
CE1
CE2
CE3
SBSRAM
Memory space CE0 is used to access 512KB of zero wait-state SBSRAM over the
C6000 external memory interface (EMI).
SBSRAM is normally set to run at the speed of the C6000 core clock, but the GC
register can be used to reduce this to one half of the core clock speed. The
appropriate setting has to be determined in conjunction with the C6000 core speed
and the external memory speed; refer to Clock Speed on page 35 for further details.
SDRAM
Memory space CE2 is used to access 16MB of SDRAM over the EMI. The SDRAM
operates at one half of the core clock speed.
FLASH
A 2MB Flash ROM device is connected to the C6000 EMI. This device is accessed,
16-bit word at a time, with word addresses from 0x0140 0000 to 0x015F FFFF using
strobe CE1 in 32-bit asynchronous mode. Each 32-bit load will give 16 bits of data in
bits 15–0 of the result; the state of bits 31–16 is undefined.
The ROM holds boot code for the C6000, configuration data for the FPGA, and
optional user-defined code.
A software protection algorithm is in place to prevent programs accidentally altering
the ROM's contents. Please contact Sundance for further information about re-
programming this device [6].
Page 10 of 53
0x00003779
For half speed SBSRAM
0x0000377D
For full speed SBSRAM (default)
0x00000040
Indicates SBSRAM
0x30FF3F23
Defines asynchronous memory timings
0x00000030
Indicates SDRAM
0x00000030
VIRTEX FPGA
SMT335E SMT375E User Manual
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