Casio CE-6800 Service Manual page 32

8. LH28F016SCT-L95A
Sym
A -A
0 20
DQ -DQ
0 7
CE#
RP#
OE#
WE#
RY/BY#
V
PP
V
cc
GND
NC
Type
INPUT ADDRESS INPUTS: Inputs for addresses during read and write operations.
Addresses are internally latched during a write cycle.
INPUT/ DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles;
OUTPUT outputs data during memory array. status register, and identifier code read
cycles. Data pins float to high-impedance when the chip is deselected or
outputs are disabled. Data is internally latched during a write cycle.
INPUT CHIP ENABLE: Activates the device's control logic, input buffers, decoders,
and sense amplifiers. CE#-high deselects the device and reduces power
consumption to standby levels.
INPUT RESET/DEEP POWER-DOWN: Puts the device in deep power-down mode
and resets internal automation. RP#-high enabies normal operation. When
driven low. RP# inhibits write operations which provides data protection during
power transitions. Exit from deep power-down sets the device to read array
mode. RP# at V
HH
configuration of block lock-bits when the master lock-bit is set. RP# = V
overrides block lock-bits theredy enabling block erase and byte write
operations to locked memory blocks. Block erase, byte write. or lock-bit
configuration with V
attempted.
INPUT OUTPUT ENABLE: Gates the device's output during a read cycle.
INPUT WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and
data are latched on the rising edge of the WE# pulse.
OUTPUT READY/BUSY#: Indicates the status of the internal WSM. When low, the
WSM is performing an internal operation (block erase, byte write, or lock-bit
configuration). RY/BY#-high indicates that the WSM is ready for new
commands, block erase is suspended, and byte write is inactive, byte write is
suspended, or the device is in deep power-down mode. RY/BY# is always
active and does not float when the chip is deselected or data outputs are
disabled.
SUPPLY BLOCK ERASE, BYTE WRITE, LOCK-BIT CONFIGURATION POWER
SUPPLY:For erasing array blocks, writing bytes, or configuring lock-bits. With
≤ V
V , memory contents cannot be altered, Block erase, byte write, and
PP PPLK
lock-bit configuration with an invalid V
spurious results and should not be attempted.
SUPPLY DEVICE POWER SUPPLY:Internal detection configures the device for 2.7 V,
3.3 V or 5 V operation. To switch from one voltage to another, ramp V
to GND and then ramp V
≤ V
With V , all write attempts to the flash memory are inhibited. Device
CC LKO
operations at invalid V
results and should not be attempted. Block erase, byte write and lock-bit
configuration operations with V
SUPPLY GROUND: Do not float any ground pins.
NO CONNECT: Lead is not internal connected: it may be driven or floated.
— 30 —
Name and Function
enables setting of the master lock-bit and enables
<RP#<V produce spurious results and should not be
HH HH
(see DC Characteristics) produce
PP
to the new voltage. Do not float any power pins.
CC
voltage (see DC Characteristics) produce spurious
CC
< 3.0 V are not supported.
CC
HH
down
CC