Siemens BS-240 Technical Description page 35

Information
Base Station System
A30808-X3247-L14-2-7618
ECU is supported by the module LTL, which provides an RF loop between downlink and
uplink path.
Signal Processing Unit (ESIPRO)
The ESIPRO-Board of the BTSPLUS is a part of the EDGE Carrier Unit. It contains the
following functions of the EDGE Carrier Unit:
– Signal Processing in uplink and downlink
– Control of RF on EPATRX
– Baseband and synthesizer frequency hopping
– Channel Control
– Radio Link Control
– O&M parts relevant for carrier unit
– Link to Core via ASIC SELIC
– Digital Modulation
– Predistortion signal processing
– Digital part of Power control
– Analog to digital conversion (RXIF)
– Digital to analog conversion (TX-baseband, TX-ramping)
– Analog to digital conversion (PDRX)
– Analog to digital conversion of Diode voltage
– Analog to digital conversion of temperature
– Local clock of CU
To understand the functional structure of ESIPRO, knowledge of the principal data flow
(see Fig. 3.9).
In uplink direction, an IF-signal with a frequency of more than 100 MHz arrives from
ERXA at the ADC (Analog Digital Converter). The ADC output is processed by a DDC
(Digital Down Converter). The DDC transforms the signal into baseband and filters the
useful part of the signal. The quasi analog signal at the output of the DDC is converted
into bits with reliability information (soft decisions) in the equalizer block. The soft deci-
sions are deciphered and decoded. Traffic channels (e.g., TCH/FS) are sent via
TRAU/PCU frames to TRAU/PCU. Signalling channels (e.g., SDCCH) are sent to the
CORE of the BTS.In downlink direction traffic channels arrive as TRAU/PCU frames
from TRAU/PCU and signaling data come from CORE. The data symbols are coded and
ciphered. Afterwards base band hopping takes place via the CC link. ESIPRO sends the
ciphered data to another ECU and receives data to be transmitted. The received data
are modulated as GMSK or 8 PSK signals and given as a base band signal to ETXA.
Both in uplink and downlink direction PLLs have to be programmed once each burst to
implement synthesizer hopping.
Technical Description (TED:BSS)
BS-240/241
35