I/O Voltage Support In The Jtag Chain - Intel MAX 10 JTAG User Manual

UG-M10JTAG | 2019.05.10
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4. I/O Voltage Support in the JTAG Chain

A JTAG chain can contain several Intel FPGA and non-Intel FPGA devices.
The
TDO
device. The devices can interface with each other although the devices may have
different V
For example, a device with 3.3-V V
3.3 V meets the minimum VIH on transistor-to-transistor logic (TTL)-level input for the
5.0-V V
CCIO
Intel MAX 10 devices can support 1.5-, 1.8-, 2.5-, or 3.3-V input levels, depending on
the V
CCIO
To interface the
V levels, insert a level shifter between the devices. If possible, construct the JTAG
CCIO
chain where device with a higher V
V level. In this setup, you only require a level shifter for shifting the
CCIO
level JTAG tester accept.
Figure 3. JTAG Chain of Mixed Voltages and Level Shifters
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pin of a device drives out at the voltage level according to the V
levels.
CCIO
device.
voltage of I/O Bank 1B.
and lines of the JTAG pins of devices that have different
TDI TDO
TDI
5.0-V
V CCIO
Tester
TDO Level
Shifter
Shift TDO to Level
Accepted by Tester
if Necessary
can drive to a device with 5.0-V V
CCIO
level drives to a device with an equal or lower
CCIO
Must be 5.0-V
Tolerant
3.3-V
V CCIO
1.5-V
V CCIO
Must be 1.8-V
Must be 2.5-V
Tolerant
of the
CCIO
because
CCIO
level to a
TDO
Must be 3.3-V
Tolerant
2.5-V
V CCIO
1.8-V 1.8-V
V CCIO V CCIO
Tolerant
ISO
9001:2015
Registered