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After debugger initialization is done and none of the above situations have
occurred, the SYSFAIL* line is negated. This indicates to the user or
VMEbus masters the state of the debugger. In a multi-computer
configuration, other VMEbus masters could view the pertinent control and
status registers to determine which CPU is asserting SYSFAIL*.
SYSFAIL* assertion/negation is also affected by the ENV command.
Refer to Appendix A for additional information.
MPU Clock Speed Calculation
The clock speed of the microprocessor is calculated and checked against a
user definable parameter housed in NVRAM (refer to the CNFG
command in Appendix A). If the check fails, a warning message is
displayed. The calculated clock speed is also checked against known clock
speeds and tolerances.
Memory Requirements
The program portion of the 162Bug is approximately 512KB of code,
consisting of download, debugger, and diagnostic packages. It is contained
entirely in Flash or PROM.
The 162Bug executes from $FF800000 whether in Flash or PROM. If you
remove the jumper at J11 pins 7 and 8, the address spaces of the Flash and
PROM are swapped. For the MVME162-2XX (MVME162LX), factory
ship configuration is with jumper J11 pins 7-8 removed (162Bug operates
out of EPROM).
The 162Bug initial stack completely changes 8KB of SRAM memory at
addresses offset $C000 from the SRAM base address, at power up or reset.
ECC DRAM mezzanines are mapped contiguously starting at zero
($00000000), largest first. With two mezzanines of the same size, the
bottom mezzanine is first.
Type of Memory Present
Single ECC DRAM mezzanine
Two ECC DRAM mezzanines
stacked
http://www.mcg.mot.com/literature
Memory Requirements
Default on-board
Default DRAM
SRAM Base
Base Address
Address
$00000000
FFE00000
$00000000
$FFE00000
3
3-11
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