Seagate BarraCuda 510 SSD Product Manual page 14

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Table 7 Pin Descriptions (continued)
Pin No. PCIe Pin
31 PETp1
32
33 GND
34
35 PERn1
36
37 PERp1
38
39 GND
40 SMB_CLK (I/O)(0/1.8V)
41 PETn0
42 SMB_DATA (I/O)(0/1.8V)
43 PETp0
44 ALERT#(O) (0/1.8V)
45 GND
46
47 PERn0
48
49 PERp0
50 PERST#(I)(0/3.3V)
51 GND
52 CLKREQ#(I/O)(0/3.3V)
53 REFCLKn
54 PEWAKE#(I/O)(0/3.3V)
55 REFCLKp
56 Reserved for MFG DATA
Seagate BarraCuda 510 SSD Product Manual, Rev A
PCIe TX Differential signal defined by the PCI Express M.2 spec
No connect
N/C
Ground
No connect
N/C
PCIe RX Differential signal defined by the PCI Express M.2 spec
No connect
N/C
PCIe RX Differential signal defined by the PCI Express M.2 spec
No connect
N/C
Ground
SMBus Clock; Open Drain with pull-up on platform
PCIe TX Differential signal defined by the PCI Express M.2 spec
SMBus Data; Open Drain with pull-up on platform.
PCIe TX Differential signal defined by the PCI Express M.2 spec
Alert notification to master; Open Drain with pull-up on platform;
Active low.
Ground
No connect
N/C
PCIe RX Differential signal defined by the PCI Express M.2 spec
No connect
N/C
PCIe RX Differential signal defined by the PCI Express M.2 spec
PE-Reset is a functional reset to the card as defined by the PCIe Mini
CEM specification.
Ground
Clock Request is a reference clock request signal as defined by the
PCIe Mini CEM specification; Also used by L1 PM Sub-states.
PCIe Reference Clock signals (100 MHz)
defined by the PCI Express M.2 spec.
PCIe PME Wake.
Open Drain with pull up on platform; Active Low.
PCIe Reference Clock signals (100 MHz)
defined by the PCI Express M.2 spec.
Manufacturing Data line. Used for SSD manufacturing only.
Not used in normal operation.
Pins should be left N/C in platform Socket.
Description
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