Rom Read Cycle And Access Parameters - NEC VR4181 mPD30181 User Manual

TClock
(internal)
ADD(21:0)
(output)
ROMCS(3:0)#
(output)
MEMRD#
(output)
DATA(15:0)
(read)
TClock
(internal)
ADD(21:3)
(output)
ADD(2:0)
(output)
ROMCS(3:0)#
(output)
DATA(15:0)
(read)
Remarks 1. ROMCS(2:0)# signals are alternated with general-purpose I/O signals and are defined as
general-purpose inputs after RTC reset. Set GPMD2REG and GPMD3REG registers in the GIU
to use them as ROMCS(2:0)#.
2. A circle in the figure indicates the sampling timing.
114
CHAPTER 6 BUS CONTROL
Figure 6-2. ROM Read Cycle and Access Parameters
(a) Ordinary ROM cycle
WROMA(3:0)
(b) PageROM cycle
Valid
WROMA(3:0)
User's Manual U14272EJ3V0UM
Valid
Valid
Valid
WPROM(2:0)
Valid
Valid
Valid