Denon DHT-FS5 Service Manual page 31

TAS5086 (7501)
Block Diagram
DVDD
DVSS
DVSS_ESD
VR_DIG
Power
VR_ANA
Supply
VR_OSC
AVDD
AVSS_PLL
VREG_EN
SDIN1
Serial
SDIN2
Data
MUX
SDIN3
Interface
SDIN4
SDIN4
MCLK
SCLK
Clock Rate
LRCLK
/Error
PLLFLTP
Detection
PLLFLTM
and PLL
HFCLK
OSCFLT
OSC_RES
SDA
Serial
Control
SCL
Interface
RESET
PDN
System
MUTE
Control
BKNDERR
(TOP VIEW)
VR_ANA
1
AVDD
2
AVSS
3
AVSS
4
PLL_FLTM
5
PLL_FLTP
6
AVSS
7
MCLK
8
RESET
9
PDN
10
DVDD
11
DVSS
12
DVSS_OSC
13
OSC_RES
14
VR_OSC
15
MUTE
16
SDA
17
SCL
18
LRCLK
19
Chan.
1 − 6
1 − 5
1− 5 L'
Channel
Down−
Selector
mix
Block
PWM_1
38
PWM_2
37
PWM_3
36
PWM_4
35
PWM_5
34
PWM_6
33
VALID2
32
VALID1
31
VR_DIG
30
DVSS
29
DVSS
28
BKND_ERR
27
SDIN1
26
SDIN2
25
SDIN3
24
SDIN4
23
SDOUT
22
RESERVED
21
SCLK
20
1 LF
MUX
L'
2 RF
MUX
R'
3 LS
4 RS
R'
5 C
MUX
(L'+R') / 2
(L'+R')/2
1− 6
Channel Six Processing
Bass Management
PWM
Control
31
DHT-FS5
6
MUX
6
MUX
6
MUX
Ch
1−6
Vol PWM 6
MUX
6
MUX
6
MUX
Downmix
I2S Serial
MUX
SDIN4 Output
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
VALID1
VALID2
SDOUT