Denon DCD-A100 Service Manual page 61

Pin No. Pin Name
60 VCC2
61 P3_0/A8(/-/D7)
62 VSS
63 P2_7/AN2_7/A7(/D7/D6)
64 P2_6/AN2_6/A6(/D6/D5)
65 P2_5/AN2_5/A5(/D5/D4)
66 P2_4/AN2_4/A4(/D4/D3)
67 P2_3/AN2_3/A3(/D3/D2)
68 P2_2/AN2_2/A2(/D2/D1)
69 P2_1/AN2_1/A1(/D1/D0)
70 P2_0/AN2_0/A0(/D0/-)
71 P1_7/D15/*INT5
72 P1_6/D14/*INT4
73 P1_5/D13/*INT3
74 P1_4/D12
75 P1_3/D11
76 P1_2/D10
77 P1_1/D9
78 P1_0/D8
79 P0_7/AN0_7/D7
80 P0_6/AN0_6/D6
81 P0_5/AN0_5/D5
82 P0_4/AN0_4/D4
83 P0_3/AN0_3/D3
84 P0_2/AN0_2/D2
85 P0_1/AN0_1/D1
86 P0_0/AN0_0/D0
87 P10_7/AN7/*KI3
88 P10_6/AN6/*KI2
89 P10_5/AN5/*KI1
90 P10_4/AN4/*KI0
91 P10_3/AN3
92 P10_2/AN2
93 P10_1/AN1
94 AVSS
95 P10_0/AN0
96 VREF
97 AVCC
98 P9_7/*ADTRG/SIN4
99 P9_6/ANEX1/SOUT4
100 P9_5/ANEX0/CLK4
( ※ 1)
32kHz
UNLOCK 64kHz
128kHz
FS0 0 1
FS1 0 0
( ※ 2)
When (68)pin is "L", version of FPGA side is acquired entering FPGA VER display mode.
pin 91 83
bit 0 1
Signal Name
+3.3V_D
FL_CS
GND
DIR1_CIDO
DIR1_CLK
DIR1_CE
DIR1_CODI
BE_UART_OK
FPGA Ver.CONT
DSDMUTE
SACD_LED_IN
P_CONT
AMUTE_IN
REMOTE
1.2V CONT
FPGA_CI
FPGA_C2
MUTE
FPGA_C3
MUTE (RSV_2)
FPGA_C4
AL32_EMPH
OPEN
AL32_TEST5
AL32_TEST4
AL32_TEST3
AL32_SIGN_SEL
OPEN
OPEN
KEY1
KEY0
OPEN
OPEN
BE_PWR_MONI
GND
MODEL_ID1
+3.3V_D
+3.3V_D
OPEN
FL_DA
FL_CLK
48kHz
44.1kHz 96kHz
192kHz
0 1
1 1
84 85
2 3
I/O Initial
O H FL Driver Chip Select
I DIR DATA OUT
O L DIR CLOCK
O L DIR CHIP ENABLE
O L DIR DATA IN
I B/E UART communication beginning notification port
O H When Ver is acquired from FPGA, it makes it to "L".
I AMUTE signal from B/E
I SACD_LED control signal judged from BE side
O L POWER ON/STANDBY control
I AMUTE signal judged from BE side (H;Mute release)
I RC input signal INT3 specification.
O H 1.2V regulator ON/OFF control for DV3.2 / MODE3_IN
O L FPGA control
I L FPGA control
O H Mute signal for RELAY control (L:Mute release)
O L FPGA control
I Compulsion MUTE from DV3.2
I FPGA control
O/(I) L FPGA emphasis selection port.
When DIR reception signal is EMPHASIS, "H"
O H DENON LINK ON/OFF control (L;ON H;OFF)
O/(I) L FPGA FS selection port
O/(I) H FPGA FS selection port
O/(I) L FPGA FS selection port
O L FPGA output signal INT/EXT selection port
O L
[non] R672 100kΩ PU
I
[non] R673 100kΩ PU
I BUTTON A/D input 1
I BUTTON A/D input 0
I [non]
I [non]
I DV3.2(BE) Power supply watch of +3.3V.
+3.0V or more is assumed to be "H"
(Distinguish by L → H, H → L, and 3.0V standard).
I MODEL ID setting(1) Sets it by resistance PULL UP/DN.
(DCD-1650SE,DCD-2010AE ; L ,
DCD-1500SE,DCD-1510AE ; H)
O L [non]
O L FL Sirial Data Out
O L FL Sirial Clock Out
61
Function