Figure 4. I/O Pins And Supported Ata Signals - Seagate ULTRA ATA ST310212A Product Manual

22
Drive pin #
Signal name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
(removed)
20
21
22
23
24
25
HDMARDY –
HSTROBE
26
27
DDMARDY–
DSTROBE
28
DMACK –
29
30
31
IOCS16 –
32
33
34
35
36
37
38
39
40
Pins 28, 34 and 39 are used for master-slave communication (details shown below).
Drive 1 (slave) Drive 0 (master)
28
34
39

Figure 4. I/O pins and supported ATA signals

U10 Family Product Manual, Rev. A
Host pin # and signal description
Reset –
1 Hardware Reset
Ground 2 Ground
DD7 3 Host Data Bus Bit 7
DD8 4 Host Data Bus Bit 8
DD6 5 Host Data Bus Bit 6
DD9 6 Host Data Bus Bit 9
DD5 7 Host Data Bus Bit 5
DD10 8 Host Data Bus Bit 10
DD4 9 Host Data Bus Bit 4
DD11 10 Host Data Bus Bit 11
DD3 11 Host Data Bus Bit 3
DD12 12 Host Data Bus Bit 12
DD2 13 Host Data Bus Bit 2
DD13 14 Host Data Bus Bit 13
DD1 15 Host Data Bus Bit 1
DD14 16 Host Data Bus Bit 14
DD0 17 Host Data Bus Bit 0
DD15 18 Device Data (15:0)
Ground 19 Ground
(No Pin)
20
DMARQ 21 DMA Request
Ground 22 Ground
DIOW– 23 Device I/O Write:
STOP Stop Ultra DMA Burst
Ground 24 Ground
DIOR –
25 Device I/O Read:
Host Ultra DMA Ready:
Host Ultra DMA Data Strobe
Ground 26 Ground
IORDY 27 I/O Channel Ready
Device Ultra DMA Ready
Device Ulta DMA Data Strobe
CSEL 28 Cable Select
29 DMA Acknowledge
Ground 30 Ground
INTRQ 31 Device Interrupt
32 Reserved
DA1 33 Host Address Bus Bit 1
PDIAG –
34 Passed Diagnostics
CBLID–
Cable Assembly Type Identifier
DA0 35 Device Address (2:0)
DA2 36 Device Address (2:0)
CS0 –
37 Chip Select (1:0)
CS1 –
38 Chip Select (1:0)
DASP –
39 Drive Active/Slave Present
Ground 40 Ground
28 CSEL
PDIAG –
34
DASP–
39
Host
28
34
39