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PC-7200
is connected to the IR2 terminal of the PIC MASTER; therefore, the
2-2-6. Bus Construction (Figure 2-1)
PIC MASTER acts as a master PIC and the PIC SLAVE acts as a
There are two buses on the main PWB; one is the address bus and
---slave1'te:-when-the-BP~-+.t-inteff~;>te<l
.... t-t"e-nlj:r.R-ter"'i"al,..ill-t - - - - t i l e otio8f is the data bus. These.buses canJulllleJ bl1.
dil'i.del!h..-__ _
returns the interrupt acknowledge status to the BCU in the SC4751
their functions. They are the address bus, data bus, and the data
by
setting
MiiO,
SO and 81 terminals to LOW. When the BCU
conversion circuit that controls these two buses.
receives this status, it recognizes that the CPU
CQuid
enter the
interrupt acknowledge cycle, and the BCU asserts the INTA signal
to the master PIC. The PIC sends the preassigned vector address
corresponding to the
110 device to the CPU via the data bus. Table
2-4 lists the assignments of the 100 to IR15 signals.
Table 2-4. Interrupt priority
Level
Function
PIC #1
IRQO
IRQ I
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ)
f
,-
.-
,-
; -
,-
,-
PCHSE
PCHEN
SCHSE
SCHEN
FOSEL
,
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t Ra9
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IRal
,
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PIC #2
Timer output 0
Keyboard interface (output buffer full)
Interrupt from PIC
#2
IRQB
Realtime clock interrupt (RTC)
IRQ9
Software redirected to IN T OAH (lRQ2 )
IRQ I 0
Reserved (option slot)
IRQII
Reserved (option slot)
IRQI2
Reserved (option slot)
IRQI3
NPX
IRQI4
HDC (option slot)
IRQI5
Reserved
Serial port
2
(UART)
Serial port 1 (UART)
Parallel port 2 (printer I/F)
FDC
Parallel port 1 (printer I/F)
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5C4752
504751
Figure 2-8. NMI and INTR control circuit
C'"
2-9
2-2-6-1. Address Bus (Figure 2-2)
This bus is classified into 3 categories of functions:
1. LAO through LA23
These bus signals are directly output from the A1 through A23
terminals of the CPU to the memory address decoding circuit.
The AD signal is used by the SC4751 to simulatively assert the
lowest bit (AAO) when the CPU performs a word access to an
8-bit device.
2. SAO through SA 19
The SA1 through SA19 are obtained by latching the A1 through
A 19 signals with the ALE Signal sent from the SC4751 at the
latches. When the O-RAM chips are being refreshed, the SC4751
outputs the refresh address from its internal counter. The SAO
signal is obtained by buffering the MO signal. The SAO through
SA 19 Signals are used to address the V-RAMs on the main PCB
and memory and an 1/0 device located on an option board. If
there is an external microprocessor on the option board, the
processor can handle resources on the main PWB, provided that
the processor outputs addresses to this bus.
3. ELA 17 through ELA23
These signals are obtained by driving the LA 17 through LA23
signals at the buffer, and they enable the 16M bytes memory
access by the CPU in the protect mode. These signals are sent
not to the devices on the main PWB but to the option slots. If
an external microprocessor on the option board utilizes the
resources on the main PWB, the processor outputs address
signals to the LA 17 through LA23 and SAO through SA 16 address
buses.
2-2-6-2. Data Bus (Figure 2-9)
Like the address bus, the data bus can be classified into the following
five categories: (Refer to Figure 2-9.)
1. LOD through L07, XOS through X015
These data bus signals are sent directly to the CPU and NPX.
And XOB through XD15 signals are provided for odd address of
the D-RAMs and ROM.
2. SOD through S07, SOS through SOlS
The SDO through 8015 signals are usually obtained by driving
the DO through 07 signals at the bi-directional buffer.
When the CPU reads data from an 8-bit device or memory, data
bus signals SOO through S07 are latched at SC4751. This is for
maintaining the first data from even address until the CPU read
the next odd address. In this case, the swap-buffer transfers an
odd address data output
to
the SOO through S07 bus lines to
the SOB through S015 bus lines. The operations mentioned
above are controlled by the data conversion circuit described in
Section 2-2-6-3.
3. XOD through X07
These bus signals are used by 1/0 devices on the main PCB
except for the FOC.
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