Ic Pin Functions - Sony HCD-V909AV Service Manual

Table of Contents

Advertisement

QQ
3 7 63 1515 0

7-20. IC PIN FUNCTIONS

• IC101 DIGITAL SIGNAL PROCESSOR (CXD2545Q)/BD board
Pin No.
Pin Name
1
SRON
2
SRDR
3
SFON
4
TFDR
5
TRON
6
TRDR
7
TFON
8
FFDR
9
FRON
10
FRDR
11
FFON
12
VCOO
13
VCOI
14
TEST
15
DV
SS
16
TES2
17
TES3
18
PDO
19
VPCO
20
VCKI
21
AVD2
TE
L 13942296513
22
IGEN
23
AVS2
24
ADIO
25
RFC
26
RFDC
27
TE
28
SE
29
FE
30
VC
31
FILO
32
FILI
33
PCO
34
CLTV
35
AVS1
36
RFAC
37
BIAS
38
ASYI
39
ASYO
40
AVD1
41
DV
DD
42
ASYE
43
www
PSSL
44
WDCK
45
LRCK
.
46
DATA
47
BCLK
48
64DATA
49
64BCLK
50
64LRCK
http://www.xiaoyu163.com
I/O
Sled drive output (Not used)
O
Sled drive output
O
Sled drive output (Not used)
O
Tracking drive output
O
Tracking drive output (Not used)
O
Tracking drive output
O
Tracking drive output (Not used)
O
Focus drive output
O
Focus drive output (Not used)
O
Focus drive output
O
Focus drive output (Not used)
O
VCO output for analog EFM (Eight to Fourteen Modulation) PLL (Not used)
O
VCO input from analog EFM PLL (Ground)
I
TEST pin connected normally to ground
I
Digital ground
TEST pin connected normally to ground
I
TEST pin connected normally to ground
I
Charge-pump output for analog EFM PLL (Not used)
O
Charge-pump output for variable pitch PLL (Not used)
O
Clock input from variable pitch external VCO (Ground)
I
Analog power supply
Power supply pin for operational amplifiers
I
Analog ground
(Not used)
I
(Not used)
O
RF signal input
I
Tracking error signal input
I
Sled error signal input
I
Focus error signal input
I
Center voltage input pin
I
Filter output for master PLL
O
Filter input for master PLL
I
Charge-pump output for master PLL
O
Control voltage input for master VCO
I
Analog ground
EFM signal input
I
Asymmetry circuit constant current input
I
Asymmetry comparate voltage input
I
EFM full swing output
O
Analog power supply
Digital power supply
Asymmetry circuit ON/OFF
I
Audio data output mode selection input
I
48-bit slot D/A interface. word clock.
O
x
ao
u163
y
48-bit slot D/A interface. LR clock.
O
i
DA 16 output when PSSL=1. 48-bit slot serial data when PSSL=0
O
DA 15 output when PSSL=1. 48-bit slot data when PSSL=0
O
O
DA 14 output when PSSL=1. 64-bit slot data when PSSL=0 (Not used)
DA 13 output when PSSL=1. 64-bit slot data when PSSL=0 (Not used)
O
DA 12 output when PSSL=1. 64-bit slot data when PSSL=0 (Not used)
O
— 80 —
http://www.xiaoyu163.com
2 9
8
Function
Q Q
3
6 7
1 3
1 5
co
.
9 4
2 8
0 5
8
2 9
9 4
2 8
m
9 9
9 9

Advertisement

Table of Contents
loading

Table of Contents