October - Intel D865GLC Manual

®
Intel Desktop Board D865GLC Specification Update
support can access sensor data and other information residing on the Desktop
Board.
NOTE
The SMBus routing to the PCI bus connectors does not conform to the PCI
Engineering Change Notice (ECN) "Addition of the SMBus to the PCI Connector
ECN", dated October 5th, 2000. The ECN specifies that SMBus signals must be
routed to all PCI bus connectors. On this board, SMBus signals are routed to
PCI bus connector 2 only.
Add-in cards that implement PCI bus connector pins A40 and A41 for any
purpose other than SMBCLK (SMBus clock) and SMBDAT (SMBus data) should
not be installed in PCI bus connector 2.
For information about
Addition of the SMBus to the PCI Connector ECN
NOTE
This document references back-panel slot numbering with respect to processor
location on the board. The AGP slot is not numbered. PCI slots are identified as
PCI slot #x, starting with the slot closest to the processor. Figure 21 (page 76)
and Figure 22 (page 77) illustrate the board's PCI slot numbering.
5. Clarification of DDR Voltage
Section 1.7, System Memory, will change as follows:
1.7 System Memory
The Desktop Boards D865GBF and D865GLC have four DIMM sockets and
support the following memory features:
•
2.6 V (only) 184-pin DDR SDRAM DIMMs with gold-plated contacts
•
Unbuffered, single-sided or double-sided DIMMs with the following
restriction:
Double-sided DIMMS with x16 organization are not supported.
24
Refer to
http://www.pcisig.com/data/s
pecifications/smb_ecn_0405
01.pdf