Embedded Debug Features - Intel Cyclone 10 GX User Manual

6. Reconfiguration Interface and Dynamic Reconfiguration
UG-20070 | 2018.09.24
You cannot merge the TX and RX channels when the Shared reconfiguration
interface parameter is enabled in the Native PHY IP core Parameter Editor. You can
merge channels only if the reconfiguration interfaces are independent.
Refer to the following two examples to merge reconfiguration interfaces.
Example 3. Using reconfiguration interface names
This example shows how to merge a transmit-only Native PHY instance with a receive-
only instance using the reconfiguration interface names. These instances are assigned
to reconfiguration group 0.
For Native PHY 0—transmit-only instance:
set_instance_assignment -name XCVR_RECONFIG_GROUP 0 -to
topdesign:topdesign_inst|<TX only instance name>*twentynm_hssi_avmm_if_inst*
For Native PHY 1—receive-only instance to be merged with Native PHY 0:
set_instance_assignment -name XCVR_RECONFIG_GROUP 0 -to
topdesign:topdesign_inst|<RX only instance name>*twentynm_hssi_avmm_if_inst*
Example 4. Using pin names
This example shows how to merge a transmit-only Native PHY instance with a receive-
only instance using pin names. These instances are assigned to reconfiguration group
1.
For Native PHY 0—transmit-only instance:
set_instance_assignment -name XCVR_RECONFIG_GROUP 1 -to tx[0]
For Native PHY 1—receive-only instance to be merged with Native PHY 0:
set_instance_assignment -name XCVR_RECONFIG_GROUP 1 -to rx[0]

6.15. Embedded Debug Features

Note: For details on TTK usage refer to "Debugging Transceiver Links" in Intel Quartus Prime
Pro Edition Handbook Volume 3: Verification.
The Cyclone 10 GX Transceiver Native PHY, ATX PLL, fPLL, and CMU PLL IP cores
provide the following optional debug features to facilitate embedded test and debug
capability:
• Altera Debug Master Endpoint (ADME)
• Optional Reconfiguration Logic
Related Information
Intel Quartus Prime Pro Edition Handbook Volume 3: Verification
(30)
The capability register is not available when merging a simplex Tx and a simplex Rx. Hence,
the user cannot check the calibration status through capability register. Please refer to
"Calibration" chapter on how to check the calibration status when merging a simplex Tx and
simplex Rx.
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