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A 32.768 kHz crystal oscillator which provides an accurate low clock frequency for the PCF50603 and
external circuitry.
For the POWER ON, the PHONE_ON pulse signal(logical low) for 200ms from PDA turns on
U204(PCF50603).
For the POWER OFF, by pressing POWER KEY of the phone application, the PHONE_ON pulse
signal(logical low) for 1s from PDA turns off U204(PCF50603) and all phone device.
The regulated voltage(U204,+VDD_GSM_CORE) is used in Core block of PCF5213.
The regulated voltage(U204,+VDD_IO_HIGH, +VDD_IO_LOW) is used in the digital part of PCF5213.
The regulated voltage(U204,+AVDD, +AVDD_HFA) is used in the analog part of PCF5213.
The regulated volgtage(U204,+VDD_RX_TX) is used in the RX and TX RF part.
The regulated Voltage(U204,+VCC_SYN) is used in the RF part.
2-2-2. Logic Part
The logic part consists of internal CPU of MODEM, Memory.
GSM MODEM(UCP201:PCF5213EL1)
The PCF5213EL1 is mainly composed of embeded DSP and ARM core.The DSP subsystem includes
the Saturn DSP core with embedded RAM and ROM, and a set of peripherals. It has 24kx16 bits
PRAM, 104k*16 bits, 32k*16 XYRAM and 63k*16 XYROM in the DSP.
The ARM946E-S consists of an ARM9E-S processor core, 8 kbyte instruction cache and 8 kbyte data
cache, tightly-coupled ITCM(Instruction Tightly Coupled Memory) and DTCM(Data Tightly Coupled
Memory)
memories,
Architecture) AHB(Advanced High-performance Bus) bus interface with a write buffer.
HD(0:15), data lines and HA(0:23), address lines are connected to S71WS256NC0(memory). It has 64
kbyte SC RAM (0.5 Mbit) and 32 kbyte SC program ROM for bootstrap loader in the ARM core.
HD(0:15), data lines and HA(0:23), address lines are connected to memory and YMU765 to
communicate. OEn, WEn control the access of memory. KROW, and KCOL recognize the key string
input status.
It has J-TAG control pins (TDI/TDO/TCK) for ARM and DSP core. J-SEL signal controls different
access to ARM and DSP core. ADC(Analog to Digital Convertor) receives battery voltage.
MCP : FLASH ROM and UtRAM (UME201:S71WS256NC0)
This system uses Spansion's memory, S71WS256NC0. The S71WS256NC0 is a Multi Chip Package
Memory which combines 256Mbit Synchronous Burst Multi Bank NOR Flash Memory and 64Mbit
Synchronous Burst U tRAM. It has 16 bit data line, HD[1~16] which is connected to PCF5213, also
has 24 bit address lines, HA[1~24]. There are 2 chip select signals, CS0n_FLASH and CS1n_RAM.
a
memory
protection
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unit,
and
an
AMBA(Advanced
2-3
Circuit Description
Microcontroller
Bus
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