Ap Soc Programmable Logic (Pl) Voltage Control; Monitoring Voltage And Current - Xilinx ZC706 User Manual

Because the rail turn on decision is made at power on time based on the presence of the J18
jumper, removing the jumper at J18 after the board is powered up does not affect the 2.5V
power delivered to the V
A jumper installed at J18 is the default setting.
In this mode the user can control when to turn on V
2.5V, 3.3V). With V
controller PMBUS along with the FMC_VADJ_ON_B signal. The combination of these allows
the user to develop code to command the V
default setting of 2.5V. Once the new V
controller U48, the FMC_VADJ_ON_B signal can be driven low by the user logic and the V
rail comes up at the new V
powers up in the V
The FMC_VADJ_ON_B signal is connected to the TCA6416APWR I
13 (see Figure 1-28). The XC7Z045 AP SoC is thus able to drive the FMC_VADJ_ON_B signal
by writing to the I²C port expander U16.
2
The I C port expander IIC_PORT_EXPANDER SDA/SCL bus is wired to the PCA9548ARGER I
U65 bus switch (see
Documentation describing PMBUS programming for the UCD90120A power controller is
available at the website

AP SoC Programmable Logic (PL) Voltage Control

All PL and PS power rails are enabled by default. When the ZC706 board is powered on, the
state of the PL_PWR_ON signal wired to 2-pin header J66 is sampled by the TI UCD90120A
controller U48. If a jumper is not installed on J66, signal PL_PWR_ON is held high, and the
TI controller U48 energizes all the PL and PS power rails.
Because the rail turn on decision is made at power on time based on the presence of the J66
jumper, installing the jumper at J66 after the board is powered up does not affect power
delivered to the any PS or PL rails, all rails remain on.
A jumper not installed at J66 is the default setting.
If a jumper is installed on J66 when the ZC706 board is powered on, signal PL_PWR_ON is
held low, and the ZC706 board does not energize the PL side power rails at power on.

Monitoring Voltage and Current

Voltage and current monitoring and control are available for selected power rails through
Texas Instruments' Fusion Digital Power Designer graphical user interface. The onboard TI
power controller (U48 at address 101) is accessed through the PMBus connector J4, which
is provided for use with the TI USB Interface Adapter PMBus pod (TI part number EVM
USB-TO-GPIO), which can be ordered from the Texas Instruments website
ZC706 Evaluation Board User Guide
UG954 (v1.5) September 10, 2015
rail and it remains on.
ADJ
off the XC7Z045 AP SoC still configures and has access to the TI
ADJ
ADJ
voltage level. Installing a jumper at J18 after a ZC706 board
ADJ
off (no jumper on J18 at ZC706 power up) mode turns on the V
ADJ
I2C Bus, page 53).
[Ref 26].
www.xilinx.com
and to which voltage level (1.8V,
ADJ
rail to be set to something other than the
ADJ
voltage level has been programmed into TI
2
Feature Descriptions
ADJ
rail.
ADJ
C port expander U16 pin
[Ref 27] and
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2
C
80