Marantz ZR6001 Service Manual page 78

IC35 : CS5361
1
RST
M/S 2
3
LRCK
4
SCLK
5
MCLK
6
VD
GND 7
8
VL
9
SDOUT
10
DIV
11
HPF
DIF 12
I/O
#
Pin Name Pin Description
I 1 Reset ( Input ) - The device enters a low power mode when low.
RST
I 2 Master/Slave Mode (Input) -In Slave mode, LRCK and SCLK become input. (FIXED LOW)
M/S
LRCK I 3 Left Right Clock ( Input ) - Determines which channel, Left or Right, is currently active on the
serial audio data line. The frequency of the left/right clock must be at the audio sample rate, Fs.
Serial Clock ( Input ) - Serial clock for the serial audio interface.
SCLK I 4
I 5 Master Clock ( Input ) - Clock source for the delta-sigma modulator and digital filters. Table 1 illustrates
MCLK
several standard audio sample rates and the required master clock frequency.
VD I 6
Digital Power ( Input ) - Positive power supply for the digital section. Refer to the Recommended Operat-
ing Conditions for appropriate voltages.
I 7,18 Ground ( Input ) - Ground reference. Must be connected to analog ground.
GND
I 8 Logic Power ( Input ) - Determines the required signal level for the digital input/output. Refer to the Rec-
VL
ommended Operating Conditions for appropriate voltages.
O 9 Serial Audio Data Output ( Output ) - Output for two's complement serial audio data.
SDOUT
I 10 MCLK Divider (Input ) - (FIXED LOW)
DIV
HPF I 11 High Pass Filter Enable (Input ) - The device includes a high pass filter after the decimator to remove
the indeterminate DC offsets introduced by the analog buffer stage and the analog modulator. The first-
order high pass filter response characteristics are detailed in the Digital Filter specifications table. The fil-
ter response scales linearly with sample rate.
DIF I 12 Digital Interface Format ( Input ) - The required relationship between the Left/Right clock, serial clock
and serial data is defined by the Digital Interface Format selection. Refer to Figures 8 and 9.
I 13,
M0 Mode Selection ( Input ) -(FIXED LOW)
M1
I 14
(FIXED LOW)
TST I 15 Test Pin (Input) - This pin needs to be connected to GND.
AINL+ I 16, Differential Left Channel Analog Input ( Input ) - Signals are presented differentially to the delta-sigma
AINL- modulators via the AINL+/- pins. The full scale differential analog input level is specified in the Analog
I 17
Characteristics Specification table.
VA I 19
Analog Power ( Input ) - Positive power supply for the analog section. Refer to the Recommended Oper-
ating Conditions for appropriate voltages.
AINR+ I 20, Differential Right Channel Analog Input ( Input ) -Signals are presented differentially to the delta-sigma
AINR- modulators via the AINR+/- pins. The full scale differential analog input level is specified in the Analog
I 21
Characteristics Specification table.
O 22 Common Mode Voltage (Output) - Nominally 2.5 volts; can be used to bias the analog input circuitry to
VCOM
the common mode voltage of the CS5361. VCOM is not buffered and the maximum current is 10 uA.
REF_GND I 23 Reference Ground ( Input ) - Ground reference for the internal sampling circuits and must be connected
to analog ground.
O 24 Positive Voltage Reference ( Output ) - Positive reference voltage for the internal sampling circuits.
FILT+
Requires the capacitive decoupling to GND as shown in the Typical Connection Diagram.
24
FILT+
23 REFGND
F ILT +
22
VCOM
21
AINR+
A IN L-
20
AINR-
A IN L+
19
VA
18 GND
17
AINL-
16
AINL+
A IN R -
15
TST
A IN R +
14
M1
13 M0
V C O M
R E F G N D
Volta ge R e fe ren ce
+
LP Filter Q
-
S /H
D A C
+
LP F ilter Q
-
S /H
D A C
96
S C L K
V L R C K S D O U T M C LK
L
S e rial O utpu t Interfa ce
H ig h
D igital
D e cim ation
P a ss
F ilter
F ilte r
H ig h
D igital
D e cim ation
P a ss
F ilter
F ilte r
R S T
D IF
M /S
H PF
D IV
M O D E 0
M O D E 1