Sanyo VPC-X1200GXR Service Manual page 4

3. IC911 (V Driver)
A V driver (IC911) is necessary in order to generate the clocks
(vertical transfer clock and electronic shutter clock) which
driver the CCD.
The XV1-XV17 signals which are output from IC101 are the
vertical transfer clocks, and the XSG1 - XSG10 signals which
are output is superimposed onto XV1, XV3, XV5, XSG7, XSG9
and XSG11 at IC911 in order to generate a ternary pulse. In
addition, the XSUB signal which is output from IC101 is used
as the sweep pulse for the electronic shutter.
TERNARY SYSTEM BLOCK
BINARY SYSTEM BLOCK
GND
V1
Level Level
V2 OV2
CH1
conversion conversion
VL
GND
Level
Level
V4 OV4
CH2 conversion
conversion
VL
GND
Level
V6 OV6 V3
conversion
CH3
conversion
VL
GND
Level
OV8
V8
conversion
CH4 conversion
VL
GND
Level
V10 OV10
V5
conversion
CH5 conversion
VL
GND
Level
V12 OV12
conversion
CH6 conversion
VL
GND
Level
V7S OV7S
conversion V7
CH7
conversion
VL
GND
Level
OV9L
V9L
conversion
CH8 conversion
VL
GND
Level
V9R OV9R
conversion
VL
GND
Level
V11L OV11L
conversion
VL
GND
Level
V11R OV11R
conversion
VL
Fig. 1-3. IC911 Block Diagram
VH VM VH VM
V9
Level
OV1A OV9A
CH9 conversion
VL VL
VH VM VH GND
Level
OV1B OV9B
CH10
conversion
VL
VL
VH VM
VH VM
V11
Level
Level OV11A
OV3A
CH11 conversion
VL VL
VH VM VH GND
Level Level
OV11B
OV3B
CH12 conversion
VL VL
VH VM
SUB SYSTEM BLOCK
Level
OV5A
VH VM SUB
VL SUB
Level
OSUB
SUBCNT conversion
VH VM
VL
Level
OV5B
VL
VH VM
Level
OV7A
VL
VH VM
Level
OV7B
VL
4. IC913 (CDS, AGC Circuit, A/D Converter and H
driver)
IC913 contains the functions of H driver, CDS, AGC and A/D
converter. As horizontal clock driver and reset pulse for CCD
image sensor are generated inside H1, H2, H3 and H4, and
output to CCD.
The video signal which is output from the CCD is input to pin
(25) of IC913. There are sampling hold blocks generated from
the SHP and SHD pulses, and it is here that CDS (correlated
double sampling) is carried out.
After passing through the CDS circuit, the signal passes
through the VGA (VGA: Variable Gain Amplifier). It is con-
verted internally into a small-amplitude actuating signal
(LVDS), and is then input to IC101. The gain of the VGA am-
plifier is controlled by pins (32), (33) and (34) using serial
signals which is output from IC101.
-3, 0, +3, +6dB
CDS
CCDIN
3V INPUT
LDO
REG
1.8V OUTPUT
RG
HORIZONTAL
HL
DRIVERS
4
H1 TO H4
GP01
GP02
Fig. 1-4. IC913 Block Diagram
- -
4
REFT REFB
AD9971
VREF
6~42 dB
12-BIT
VGA REDUCED
ADC
RANGE
LVDS
OUTPUT
CLAMP
INTERNAL
CLOCKS
PRECISION
INTERNAL
TIMING
REGISTERS
GENERATOR
SYNC
GENERATOR
HD VD CLI
TCLKP
TCLKN
DOUT0P
DOUT0N
DOUT1P
DOUT1N
SL
SCK
SDATA