Transmit Inhibit - Vertex Standard VXA-700 Service Manual

Circuit Description
The filtered 2nd IF signal from ceramic filter CF2001 is
applied to the limiter amplifier section of Q2023, which
removes amplitude variations in the 10.7 MHz IF before
detection of the speech by the detector (which includes
coil L2002 and capacitor C2061). Detected audio from
Q2023 is passed through the de-emphasis network, con-
sisting of resistors R2051, R2053, R2054, and R2074, ca-
pacitors C2048, C2049, C2050, and C2063, and Q2020-2
(NJM2904V); the audio is then applied to the AF amplifi-
er, Q2010 (TDA7233D).
Squelch Control
When a signal is received, a DC squelch control voltage
appears at pin 12 of FM IF subsystem IC Q2039 at a level
according to the received signal strength. This DC is ap-
plied to pin 13 of microprocessor Q3026 (LC87F52C8A).
The DC squelch control voltage is compared with the SQL
threshold level by the microprocessor, Q3026. If the DC
squelch control voltage is higher, pin 46 of Q3026 goes
high. This signal activates the AF MUTE gate Q2014
(DTC143ZE), thus disabling the receiver audio.
If a signal strong enough to exceed the threshold level is
received the microprocessor stops scanning, if scanning
is engaged, and allows audio to pass through the AF
MUTE gate Q2014.
Transmit Signal Path
Speech input from the microphone is passed through mi-
crophone amplifier Q3006-3 (NJM2902V), then applied
to the ALC amplifier Q3011 (AN5123MS).
In the AM mode, the amplified speech signal is passed
through the low-pass filter Q3006-2 (NJM2902V) and
high-pass filter Q3012-1 (NJM2904V). The filtered speech
signal is passed through Q3013 (M62364FP), which ad-
justs the modulation level, then fed to the AM modulator
Q1037 (2SK2974).
In the FM mode, the amplified speech signal is passed
through the low-pass filter Q3006-2 (NJM2902V) and
high-pass filter Q3006-4 (NJM2902V), where the signal
is pre-emphasized and stripped of excessive high frequen-
cy components that might result in over-deviation.
The processed audio may be mixed with a CTCSS tone
generated by the microprocessor Q3026, and the level is
controlled by Q3013 (M62364FP). The audio is then de-
livered to D1005 (HSU277) for frequency-modulation of
the PLL carrier up to 5 kHz from the un-modulated carri-
er at the transmitting frequency.
When using the optional headset, the SIDETONE signal
from J2001 becomes "HIGH," turning pin 18 of Q3026 on;
pin 56 of Q3026 then goes "HIGH," routing a portion of
the speech to the AF power amplifier Q2010 as a monitor
signal.
8
The carrier signal from the VCO Q1014 (2SC5555) passes
through buffer amplifier Q1017 (2SC5555) and TX/RX
switch D1010 (HSU277)
The signal from D1010 is amplified by Q1029 (2SC3356),
and Q1031 (2SK2973), and ultimately applied to the final
amplifier Q1037 (2SK2974) which increases the signal lev-
el up to 5 watts output power. The transmit signal then
passes through the antenna switch D1016 (RLS135), and
is low-pass filtered to suppress away harmonic spurious
radiation before delivery to the antenna.
Automatic Transmit Power Control
RF power output from the final amplifier is sampled by
C1149/C1154 and is rectified by D1021 (HMS86WA). The
resulting DC is fed through the Automatic Power Con-
troller Q3012 (NJU7018U), thus allowing control of the
power output.

Transmit Inhibit

When the transmit PLL is unlocked, pin 7 of PLL chip
Q1013 (MB15A01PFV1) goes to a logic "low." The result-
ing DC "unlock" control voltage is turns off TX inhibit
switches Q1016 (2SA1602A), Q1018 (UMW1), and Q1020
(DTA143EE) to disable the supply voltage to transmitter
RF amplifier Q1029, disabling the transmitter.
Spurious Suppression
Generation of spurious products by the transmitter is min-
imized by the fundamental carrier frequency being equal
to the final transmitting frequency. Additional harmonic
suppression is provided by a low-pass filter consisting of
L1030, L1035, and L1036 and C1147, C1153, C1155, C1159,
C1164, and C1167, resulting in more than 60 dB of har-
monic suppression prior to delivery of the RF signal to
the antenna.
PLL Frequency Synthesizer
The PLL circuitry consists of VCO Q1014 (2SC5555), VCO
buffers Q1017 and Q1021 (both 2SC5555), and PLL sub-
system IC Q1013 (MB15A01PFV1), which contains a ref-
erence divider, serial-to-parallel data latch, programma-
ble divider, phase comparator, and charge pump.
Stability is maintained by a regulated 3.5 V supply via
Q3023 (2SB1132Q) and Q3024 (S-812C35AUA-C2P),
which feeds the PLL reference oscillator Q2030
(2SC4116GR), as well as capacitors associated with the
17.475 MHz frequency reference crystal X2001.
In the receive mode, VCO Q1014 oscillates between 133.65
and 199.4 MHz. The VCO output is buffered by Q1017
and Q1021, and applied to the prescaler section of Q1013.
There the VCO signal is divided by 64 or 65, according to
a control signal from the data latch section of Q1013, be-
fore being applied to the programmable divider section
of Q1013. The data latch section of Q1013 also receives