1 Semiconductor
Bank Interleave Random Row Read/Write Cycle @CAS
0
1
2
3
CLK
CKE
CS
RAS
CAS
ADDR
RAa
CAa
A11
A10
RAa
DQ
WE
UDQM,
LDQM
Row Active
(A-Bank)
Read Command
(A-Bank)
4
5
6
7
8
High
RBb
RBb
QAa0 QAa1 QAa2 QAa3
Row Active
Write Command
(B-Bank)
Precharge Command
(A-Bank)
CAS Latency=2, Burst Length=4
CAS
CAS
9
10
11
12
13
14
CBb
RAc
CAc
RAc
QBb0 QBb1 QBb2 QBb3
Read Command
(B-Bank)
(A-Bank)
Row Active
(A-Bank)
FEDD56V16160F-02
MSM56V16160F
15
16
17
18
19
QAc0 QAc1 QAc2 QAc3
19/31