Huawei G510 Maintenance Manual page 45

G510 Maintenance Manual V1.0 INTERNAL
Figure 9-11 shows the circuit diagram of the 32.768 kHz clock.
Figure 9-11 Circuit diagram of the 32.768 kHz clock
Analysis
Figure 9-12 shows the block diagram of the 19.2 MHz clock.
Figure 9-12 Block diagram of the 19.2 MHz clock
As shown in Figure 9-12, the 19.2 MHz clock outputs clock signals to the PM8029 and
RTR6285A. The TPK_LO_ADJ controls the clock output precision. The TPK_LO_ADJ has
two levels of filtering circuits: from R204 to C232 and from R3101 to C3101. The
TPK_LO_ADJ outputs clock signals to the PM8029 and then to the main chip as the system
main clock.
The 32.768 kHz oscillator outputs signals to the PM8029, which provides signals to the
system.
2013-01-28
Huawei Confidential Page 45 of 96