Sony SCD-C555ES Service Manual page 46

SCD-C555ES
Pin No. Pin Name
132 FDO
133, 134 GNDA2, GNDA1
135 SPO
136 VC2
137 MDIN2
138 MDIN1
139 VCCA1
140 CLVS
141 VSS
142 MDSOUT
143 VDD
144 MDPOUT
145 DEFECT
146 GSCOR
147 EXCK
148 SBIN
149 VSS
150 SCOR
151 WFCK
152 VDD5V
153 XRCI
154 VDDS
155 C2PO
156 VDD
157 DBCK
158 BCLK
159 DDAT
160 MDAT
161 VSS
162 DLRC
163 LRCK
164 XRST
165 IFS0
166 IFS1
167 XTAL
168 VSS
169 XTA2
170 XTA1
171 VDD
172 to 176 D0 to D4
46
I/O
O Signal output from the charge pump for frequency comparator
— Ground terminal (analog system)
O Spindle motor (M3) control signal output to the BA5912AFP (IC512)
I Middle point voltage (+1.65V) input terminal
I Spindle motor (M3) control signal input from the CXD3008Q (IC509)
I MDP input terminal
— Power supply terminal (+3.3V) (analog system)
O Control signal output for selection the spindle control filter at CLVS
— Ground terminal (digital system)
O Frequency error output terminal of internal CLV circuit
— Power supply terminal (+3.3V) (digital system)
O Phase error output terminal of internal CLV circuit
I Defect signal input terminal Not used (fixed at "L" )
I Guard subcode sync OR signal input from the CXD3008Q (IC509)
O Subcode serial data reading clock signal output to the CXD3008Q (IC509)
I Subcode serial data input from the CXD3008Q (IC509)
— Ground terminal (digital system)
I Subcode sync OR signal input from the CXD3008Q (IC509)
I Write frame clock signal input from the CXD3008Q (IC509)
— Power supply terminal (+5V)
I RAM overflow signal input terminal Not used (fixed at "L")
— Power supply terminal (+5V) (digital system)
I C2 pointer signal input from the CXD3008Q (IC509)
— Power supply terminal (+3.3V) (digital system)
O Bit clock signal (2.8224 MHz) output terminal Not used (open)
I Bit clock signal (2.8224 MHz) input from the CXD3008Q (IC509)
O PCM data output terminal Not used (open)
I Serial data input from the CXD3008Q (IC509)
— Ground terminal (digital system)
O L/R sampling clock signal (44.1 kHz) output terminal Not used (open)
I L/R sampling clock signal (44.1 kHz) input from the CXD3008Q (IC509)
I Reset signal input from the expander (IC902) "L": reset
I Interface select signal input terminal Fixed at "L" in this set
I Interface select signal input terminal Fixed at "H" in this set
I 33.86688 MHz clock signal input terminal
— Ground terminal (digital system)
O System clock output terminal (33.86688 MHz)
I System clock input terminal (33.86688 MHz)
— Power supply terminal (+3.3V) (digital system)
I/O Two-way data bus with the CPU (IC901) and expander (IC902)
Description