JVC TH-A30 Service Manual page 24

TH-A30
M12L64164A (AU13, AU14) : SDRAM
1.Pin layout
VDD 1
DQ0 2
VDDQ 3
DQ1 4
DQ2 5
VSSQ 6
DQ3 7
DQ4 8
VDDQ 9
DQ5 10
DQ6 11
VSSQ 12
DQ7 13
VDD 14
L D Q M 15
W E 16
C A S 17
R A S 18
C S 19
A13 20
A12 21
A10/AP 22
A0 23
A1 24
A2 25
A3 26
VDD 27
3.Block diagram
CLK
Clock
Generator
CKE
Address
CS
RAS
CAS
WE
1-24
54 VSS
53 DQ15
52 VSSQ
51 DQ14
50 DQ13
49 VDDQ
48 DQ12
47 DQ11
46 VSSQ
45 DQ10
44 DQ9
43 VDDQ
42 DQ8
41 VSS
40 N C
39 U D Q M
38 CLK
37 CKE
36 N C
35 A11
34 A9
33 A8
32 A7
31 A6
30 A5
29 A4
28 VSS
Row
Address
Buffer
Mode
&
Register
Refresh
Counter
Column
Address
Buffer
&
Refresh
Counter
2.Pin function
Symbol Function
CLK System Clock
CS Chip Select
CKE Clock Enable
A0 ~ A11 Address
A12 , A13 Bank Select Address
RAS Row Address Strobe
CAS Column Address Strobe
WE Write Enable
L(U)DQM Data Input / Output Mask
DQ0 ~ DQ15 Data Input / Output
VDD / VSS Power Supply / Ground
VDDQ / VSSQ Data Output Power / Ground
NC No Connection
Bank C
Bank B
Bank A
Sense Amplifier
Column Decoder
Data Control Circuit
Bank D
L(U)DQM
DQ