JVC TH-A30 Service Manual page 17

2. Pin function
Name
IRRX1/GPIO0
IDC_CL/GPIO18
IDC_DA/GPIO19
RTS1/GPIO20
RXD1/GPIO21
TXD1/GPIO22
CTS1/GPIO23
RTS2/SPI_CLK/
GPIO37
RXD2/SPI_MISO/
GPIO38
TXD2/SPI_MOSI/
GPIO39
CTS2/SPI_CS/
GPIO40
TRST
TDO
TDI/GPI0
TMS/GPI1
TCK
1. I - input, O - output, OD - open drain, PU - requires external pull-up resistor.
3. Block diagram
Parallel/serial
Track Buffer
DVD Interface Processor
Audio
I2S Stereo In
Input Unit
ASYNC BUS IR GPIO SPI UART1&2
Remote Control
Pin No. Type
28 I
160 I/O
161
162 O
163 I
164 O
165 I
185 O
186 I
187 O
188 I
197 I
198 O
199 I
200 I
201 I
SDRAM Controller
Decryption
ZiVA
A/V Core
System Control Bus
Bus Interface Unit
ATAPI
1
Description
IR Remote Receive. This input connects to an integrated (photo diode,
band pass, demodulator) IR receiver. General Purpose I/O 0
Serial clock signal for IDC data transfer. It should be pulled up to the
positive supply voltage, depending on the device) using an external
pull-up resistor. General Purpose I/O [18]
Serial data signal for IDC data transfer. It should be pulled up to the supply
voltage using an external pull-up resistor. General Purpose I/O [19]
Ready to send, UART1
General Purpose I/O [20]
Receive data, UART1
General Purpose I/O [21]
Transmit data, UART1
General Purpose I/O [22]
Clear to send, UART1
General Purpose I/O [23]
Ready to send, UART2
Serial Peripheral Interface Clock
General Purpose I/O [37]
Receive data, UART2
Serial Peripheral Interface - Master Input/Slave Output
General Purpose I/O [38]
Transmit data, UART2
Serial Peripheral Interface - Master Output/Slave Input
General Purpose I/O [39]
Clear to send, UART2
Serial Peripheral Interface ????
General Purpose I/O [40]
Test reset. BST reset - resets the TAP controller.
This signal must be pulled low.
Test data Out. BST serial data output.
Test data In. BST serial data chain input.
General Purpose Input pin 0.
Test mode select. Controls state of test access port (TAP) controller.
General Purpose Input pin 1.
Test clock. Boundary scan test (BST) serial data clock.
32-128Mbit
SDRAM
Interlaced/
Graphics
Progressive
Engine
Video
Encoder
SPARC
Microprocessor
Phase
Lock
IDC
JTAG Interface
Loop
13.5 MHz Crystal
CCIR 656
Digital Video
Composite
Five 10-bit
Y/R
Video
C
DACs
Cr/Pr/G
Cb/Pb/B
IEC 958/1937
Audio
Downmix
Output
Left/right
Unit Center/subwoofer
Left/ right/surround
TH-A30
(4/4)
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